设计了一种具有较高输出功率和较高功率效率的B类功率放大器,采用了负载牵引和源牵引的设计方法得出最大输出功率对应的最优负载阻抗和源阻抗,并运用阻抗匹配技术分别实现负载阻抗和源阻抗到50Ω的匹配电路设计.仿真结果表明,工作频率为...设计了一种具有较高输出功率和较高功率效率的B类功率放大器,采用了负载牵引和源牵引的设计方法得出最大输出功率对应的最优负载阻抗和源阻抗,并运用阻抗匹配技术分别实现负载阻抗和源阻抗到50Ω的匹配电路设计.仿真结果表明,工作频率为960 MHz下该功率放大器的功率附加效率为69.39%,输出功率为45.32 d Bm.展开更多
In this paper, a new principle for an adaptive line driver using Fuzzy logic is presented. This type of line driver can adapt its output impedance and gain, automatically to the applied load using a fuzzy logic contro...In this paper, a new principle for an adaptive line driver using Fuzzy logic is presented. This type of line driver can adapt its output impedance and gain, automatically to the applied load using a fuzzy logic controller (FLC). This results in automatically corrected output impedance for different cables with terminations. Also, the line driver output impedance and gain become insensitive to process and line variations. As an example, a line driver for ADSL application has been designed. The circuit operates from a 3.3 v in a 0.35 um standard CMOS technology. The power consumption of FLC is about 1 mW. The circuit dissipates 106 mW and exhibits a -62 dB THD for a 3.2-Vpp signal at 5 MHz across a 75 ohms Load. It has a relatively high -3 dB bandwidth (240 MHz) with good phase margin of about 67 degrees in a 10 pF load capacitor.展开更多
文摘设计了一种具有较高输出功率和较高功率效率的B类功率放大器,采用了负载牵引和源牵引的设计方法得出最大输出功率对应的最优负载阻抗和源阻抗,并运用阻抗匹配技术分别实现负载阻抗和源阻抗到50Ω的匹配电路设计.仿真结果表明,工作频率为960 MHz下该功率放大器的功率附加效率为69.39%,输出功率为45.32 d Bm.
文摘In this paper, a new principle for an adaptive line driver using Fuzzy logic is presented. This type of line driver can adapt its output impedance and gain, automatically to the applied load using a fuzzy logic controller (FLC). This results in automatically corrected output impedance for different cables with terminations. Also, the line driver output impedance and gain become insensitive to process and line variations. As an example, a line driver for ADSL application has been designed. The circuit operates from a 3.3 v in a 0.35 um standard CMOS technology. The power consumption of FLC is about 1 mW. The circuit dissipates 106 mW and exhibits a -62 dB THD for a 3.2-Vpp signal at 5 MHz across a 75 ohms Load. It has a relatively high -3 dB bandwidth (240 MHz) with good phase margin of about 67 degrees in a 10 pF load capacitor.