A novel slow-down set waveform is proposed to improve the set performance and a 1 kb phase change random access memory chip fabricated with a 13nm CMOS technology is implemented to investigate the set performance by d...A novel slow-down set waveform is proposed to improve the set performance and a 1 kb phase change random access memory chip fabricated with a 13nm CMOS technology is implemented to investigate the set performance by different set programming strategies based on this new set pulse. The amplitude difference （I1 - I2） of the set pulse is proved to be a crucial parameter for set programming. We observe and analyze the cell characteristics with different I1 - I2 by means of thermal simulations and high-resolution transmission electron microscopy, which reveal that an incomplete set programming will occur when the proposed slow-down pulse is set with an improperly high I1 - I2. This will lead to an amorphous residue in the active region. We also discuss the programming method to avoid the set performance degradations.展开更多
We investigate the effect of the formation process under pulse and dc modes on the performance of one transistor and one resistor （1 T1R） resistance random access memory （RRAM） device. All the devices are operated...We investigate the effect of the formation process under pulse and dc modes on the performance of one transistor and one resistor （1 T1R） resistance random access memory （RRAM） device. All the devices are operated under the same test conditions, except for the initial formation process with different modes. Based on the statistical results, the high resistance state （FIRS） under the dc forming mode shows a lower value with better distribution compared with that under the pulse mode. One of the possible reasons for such a phenomenon originates from different properties of conductive filament （CF） formed in the resistive switching layer under two different modes. For the dc forming mode, the formed filament is thought to be continuous, which is hard to be ruptured, resulting in a lower HRS. However, in the case of pulse forming, the filament is discontinuous where the transport mechanism is governed by hopping. The low resistance state （LRS） can be easily changed by removing a few trapping states from the conducting path. Hence, a higher FIRS is thus observed. However, the HRS resistance is highly dependent on the length of the gap opened. A slight variation of the gap length will cause wide dispersion of resistance.展开更多
基金Supported by the Strategic Priority Research Program of Chinese Academy of Sciences under Grant No XDA09020402the National Key Basic Research Program of China under Grant Nos 2013CBA01900,2010CB934300,2011CBA00607,and 2011CB932804+2 种基金the National Integrate Circuit Research Program of China under Grant No 2009ZX02023-003the National Natural Science Foundation of China under Grant Nos 61176122,61106001,61261160500,and 61376006the Science and Technology Council of Shanghai under Grant Nos 12nm0503701,13DZ2295700,12QA1403900,and 13ZR1447200
文摘A novel slow-down set waveform is proposed to improve the set performance and a 1 kb phase change random access memory chip fabricated with a 13nm CMOS technology is implemented to investigate the set performance by different set programming strategies based on this new set pulse. The amplitude difference （I1 - I2） of the set pulse is proved to be a crucial parameter for set programming. We observe and analyze the cell characteristics with different I1 - I2 by means of thermal simulations and high-resolution transmission electron microscopy, which reveal that an incomplete set programming will occur when the proposed slow-down pulse is set with an improperly high I1 - I2. This will lead to an amorphous residue in the active region. We also discuss the programming method to avoid the set performance degradations.
基金Supported by the National Basic Research Program of China under Grant Nos 2011CBA00602,2010CB934200,2011CB921804,2011CB707600,2011AA010401,and 2011AA010402the National Natural Science Foundation of China under Grant Nos61322408,61334007,61376112,61221004,61274091,61106119,61106082,and 61006011
文摘We investigate the effect of the formation process under pulse and dc modes on the performance of one transistor and one resistor （1 T1R） resistance random access memory （RRAM） device. All the devices are operated under the same test conditions, except for the initial formation process with different modes. Based on the statistical results, the high resistance state （FIRS） under the dc forming mode shows a lower value with better distribution compared with that under the pulse mode. One of the possible reasons for such a phenomenon originates from different properties of conductive filament （CF） formed in the resistive switching layer under two different modes. For the dc forming mode, the formed filament is thought to be continuous, which is hard to be ruptured, resulting in a lower HRS. However, in the case of pulse forming, the filament is discontinuous where the transport mechanism is governed by hopping. The low resistance state （LRS） can be easily changed by removing a few trapping states from the conducting path. Hence, a higher FIRS is thus observed. However, the HRS resistance is highly dependent on the length of the gap opened. A slight variation of the gap length will cause wide dispersion of resistance.
