A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It...A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2 μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.展开更多
A three-transistor active pixel sensor and its double sampling readout circuit implemented by a switch capacitor amplifier are designed. The circuit is embedded in a 64 × 64 pixel array CMOS image sensor and succ...A three-transistor active pixel sensor and its double sampling readout circuit implemented by a switch capacitor amplifier are designed. The circuit is embedded in a 64 × 64 pixel array CMOS image sensor and success-fully taped out with a Chartered 0.35μm process. The pixel pitch is 8μm × 8μm with a fill factor of 57%, the photo-sensitivity is 0.8V/（lux · s） ,and the dynamic range is 50dB. Theoretical analysis and test results indicate that as the process is scaled down, a smaller pixel pitch reduces the sensitivity. A deep junction n-well/p-substrate photodiode with a reasonable fill factor and high sensitivity are more appropriate for submicron processes.展开更多
A double sampling circuit to eliminating fixed pattern noise(FPN) in CMOS image sensor (CIS) is presented. Double sampling is implemented by column switch capacitor amplifier directly, and offset compensation is added...A double sampling circuit to eliminating fixed pattern noise(FPN) in CMOS image sensor (CIS) is presented. Double sampling is implemented by column switch capacitor amplifier directly, and offset compensation is added to the amplifier to suppress column FPN. The amplifier is embedded in a 64×64 CIS and successfully fabricated with chartered 0.35 μm process. Theory analysis and circuit simulation indicate that FPN can be suppressed from millivolt to microvolt. Test results show that FPN is smaller than one least-significant bit of 8 bit ADC. FPN is reduced to an acceptable level with double sampling technique implemented with switch capacitor amplifier.展开更多
A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 4...A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 43%,higher than the traditional factor of 30%. Moreover, compared with the conventional method whose fixed pattern noise （FPN） is around 0.5%, a dynamic digital double sampling technique is developed, which possesses simpler circuit architecture and a better FPN suppression outcome. The CMOS image sensor chip is implemented in the 0.35μm mixed signal process of a Chartered by MPW. The experimental results show that the chip operates welt,with an FPN of about 0.17%.展开更多
电子轰击有源像素传感器(electron bombarded active pixel sensor,EBAPS)是一种新型的真空-固体混合型微光夜视器件,而调制传递函数(modulation transfer function,MTF)作为EBAPS的性能参数之一,能够反映成像系统对不同频率成分的传递...电子轰击有源像素传感器(electron bombarded active pixel sensor,EBAPS)是一种新型的真空-固体混合型微光夜视器件,而调制传递函数(modulation transfer function,MTF)作为EBAPS的性能参数之一,能够反映成像系统对不同频率成分的传递能力,但目前国内缺少相应的测试手段。因此,为了表征并评价EBAPS的成像质量,基于像增强器狭缝法测试MTF的原理,设计并搭建了一套EBAPS的MTF测试系统。通过驱动EBAPS器件,利用USB接口将采集到的数据传输至上位机进行图像分析,对狭缝图像进行处理获得线扩散函数(line spread function,LSF),经离散傅里叶变换后得到相应的调制传递函数曲线。在狭缝靶标处照度为2×10^(-2) lx时,一定范围内随着电压升高,EBAPS的MTF先升高后降低,且在外加-1 000 V时取得最大值。在光成像模式下,微调狭缝与传感器成像面的相对位置,连续5次测试得到几个重要频率点的MTF值的标准差均低于0.01,稳定性较好。展开更多
A wide-dynamic-range CMOS image sensor（CIS） based on synthesis of a long-time and a short-time exposure signal in the floating diffusion（FD） of a five-transistor active pixel is proposed.With optimized pixel opera...A wide-dynamic-range CMOS image sensor（CIS） based on synthesis of a long-time and a short-time exposure signal in the floating diffusion（FD） of a five-transistor active pixel is proposed.With optimized pixel operation,the response curve is compressed and a wide dynamic range image is obtained.A prototype wide-dynamic-range CMOS image sensor was developed with a 0.18μm CIS process.With the double exposure time 2.4 ms and 70 ns,the dynamic range of the proposed sensor is 80 dB with 30 frames per second（fps）.The proposed CMOS image sensor meets the demands of applications in security surveillance systems.展开更多
文摘A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2 μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.
文摘A three-transistor active pixel sensor and its double sampling readout circuit implemented by a switch capacitor amplifier are designed. The circuit is embedded in a 64 × 64 pixel array CMOS image sensor and success-fully taped out with a Chartered 0.35μm process. The pixel pitch is 8μm × 8μm with a fill factor of 57%, the photo-sensitivity is 0.8V/（lux · s） ,and the dynamic range is 50dB. Theoretical analysis and test results indicate that as the process is scaled down, a smaller pixel pitch reduces the sensitivity. A deep junction n-well/p-substrate photodiode with a reasonable fill factor and high sensitivity are more appropriate for submicron processes.
基金Supported by National Natural Science Foundation of China (No.60576025).
文摘A double sampling circuit to eliminating fixed pattern noise(FPN) in CMOS image sensor (CIS) is presented. Double sampling is implemented by column switch capacitor amplifier directly, and offset compensation is added to the amplifier to suppress column FPN. The amplifier is embedded in a 64×64 CIS and successfully fabricated with chartered 0.35 μm process. Theory analysis and circuit simulation indicate that FPN can be suppressed from millivolt to microvolt. Test results show that FPN is smaller than one least-significant bit of 8 bit ADC. FPN is reduced to an acceptable level with double sampling technique implemented with switch capacitor amplifier.
文摘A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 43%,higher than the traditional factor of 30%. Moreover, compared with the conventional method whose fixed pattern noise （FPN） is around 0.5%, a dynamic digital double sampling technique is developed, which possesses simpler circuit architecture and a better FPN suppression outcome. The CMOS image sensor chip is implemented in the 0.35μm mixed signal process of a Chartered by MPW. The experimental results show that the chip operates welt,with an FPN of about 0.17%.
基金supported by the National Natural Science Foundation of China(Nos.60806010,60976030)the Tianjin Innovation Special Funds for Science and Technology,China(No.05FZZDGX00200).
文摘A wide-dynamic-range CMOS image sensor（CIS） based on synthesis of a long-time and a short-time exposure signal in the floating diffusion（FD） of a five-transistor active pixel is proposed.With optimized pixel operation,the response curve is compressed and a wide dynamic range image is obtained.A prototype wide-dynamic-range CMOS image sensor was developed with a 0.18μm CIS process.With the double exposure time 2.4 ms and 70 ns,the dynamic range of the proposed sensor is 80 dB with 30 frames per second（fps）.The proposed CMOS image sensor meets the demands of applications in security surveillance systems.
