This paper presents a new topology to implement Class F power amplifier for eliminating the on-resistance (R_(ON))effect.The time-domain and frequency-domain voltage and current waveforms for Class F amplifier are ana...This paper presents a new topology to implement Class F power amplifier for eliminating the on-resistance (R_(ON))effect.The time-domain and frequency-domain voltage and current waveforms for Class F amplifier are ana- lyzed using Fourier series analysis method.Considering the on-resistance effect,the formulas of the efficiency,output power,dc power dissipation,and fundamental load impedance are given from ideal current and voltage waveforms.For experimental verification,we designed and implemented a Class F power amplifier,which operates at 850 MHz using MGaAs/GaAs Heterostructure FET(HFET)device,and analyzed the measurement results.Test results show that the maximum PAE of 67% can be achieved at 28 dBm output power level.展开更多
采用0.13μm Si Ge双极互补型金属氧化物半导体（Bi CMOS）工艺,设计了一款X波段功率放大器芯片。通过采用共射共基放大器电路结构和有源线性化偏置电路,提高了电路耐压值和功放最大输出功率。通过两级共射共基放大电路级联,结合级间匹...采用0.13μm Si Ge双极互补型金属氧化物半导体（Bi CMOS）工艺,设计了一款X波段功率放大器芯片。通过采用共射共基放大器电路结构和有源线性化偏置电路,提高了电路耐压值和功放最大输出功率。通过两级共射共基放大电路级联,结合级间匹配电路及输出匹配电路,提高了放大器的增益和工作带宽。采用非均匀功率管版图布局及镇流电阻,提升功率放大器电路可靠性。测试结果表明,在8-12 GHz频段内,放大器回波损耗均小于-10 d B,小信号增益大于30 d B,1 d B压缩点输出功率为16 d Bm,饱和功率大于19 d Bm,峰值饱和功率附加效率大于18%。该放大器工作在AB类,采用5 V供电,静态工作电流为80 m A,面积为1.22 mm×0.73 mm。展开更多
基于IBM SOI 0.18μm CMOS工艺,设计了一种高功率附加效率(PAE)的E类功率放大器,由驱动级和输出级两级构成。驱动级采用E类结构,使输出级能更好地实现开与关。输出级采用电感谐振寄生电容,提高了效率。输出级的共栅管采用自偏置的方式,...基于IBM SOI 0.18μm CMOS工艺,设计了一种高功率附加效率(PAE)的E类功率放大器,由驱动级和输出级两级构成。驱动级采用E类结构,使输出级能更好地实现开与关。输出级采用电感谐振寄生电容,提高了效率。输出级的共栅管采用自偏置的方式,防止晶体管被击穿。两级之间使用了改善输出级电压和电流交叠的网络。仿真结果表明,在2.8 V电源电压下,工作频率为2.4 GHz时,功率放大器的输出功率为23.17 d Bm,PAE为57.7%。展开更多
文摘This paper presents a new topology to implement Class F power amplifier for eliminating the on-resistance (R_(ON))effect.The time-domain and frequency-domain voltage and current waveforms for Class F amplifier are ana- lyzed using Fourier series analysis method.Considering the on-resistance effect,the formulas of the efficiency,output power,dc power dissipation,and fundamental load impedance are given from ideal current and voltage waveforms.For experimental verification,we designed and implemented a Class F power amplifier,which operates at 850 MHz using MGaAs/GaAs Heterostructure FET(HFET)device,and analyzed the measurement results.Test results show that the maximum PAE of 67% can be achieved at 28 dBm output power level.
基金Supported by the National Natural Science Foundation of China (61822407,62074161,62004213)the National Key Research and Development Program of China under (2018YFE0125700)。
文摘采用0.13μm Si Ge双极互补型金属氧化物半导体（Bi CMOS）工艺,设计了一款X波段功率放大器芯片。通过采用共射共基放大器电路结构和有源线性化偏置电路,提高了电路耐压值和功放最大输出功率。通过两级共射共基放大电路级联,结合级间匹配电路及输出匹配电路,提高了放大器的增益和工作带宽。采用非均匀功率管版图布局及镇流电阻,提升功率放大器电路可靠性。测试结果表明,在8-12 GHz频段内,放大器回波损耗均小于-10 d B,小信号增益大于30 d B,1 d B压缩点输出功率为16 d Bm,饱和功率大于19 d Bm,峰值饱和功率附加效率大于18%。该放大器工作在AB类,采用5 V供电,静态工作电流为80 m A,面积为1.22 mm×0.73 mm。
文摘基于IBM SOI 0.18μm CMOS工艺,设计了一种高功率附加效率(PAE)的E类功率放大器,由驱动级和输出级两级构成。驱动级采用E类结构,使输出级能更好地实现开与关。输出级采用电感谐振寄生电容,提高了效率。输出级的共栅管采用自偏置的方式,防止晶体管被击穿。两级之间使用了改善输出级电压和电流交叠的网络。仿真结果表明,在2.8 V电源电压下,工作频率为2.4 GHz时,功率放大器的输出功率为23.17 d Bm,PAE为57.7%。
