Area-Optimized BCD-4221 VSLI Adder Architecture for High-Performance Computing

Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Large Scale Integration),the full adder is a basic component as it plays a major role in designing the integrated circuits applications.To minimize the power,various adder designs are implemented and each implemented designs undergo defined drawbacks.The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more.To overcome such issues and to obtain better performance,a novel parallel adder is proposed.The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability.This proposed novel parallel adder is attained from the carry look-ahead adder.The merits of this suggested adder are better speed,power consumption and delay,and the capability in driving.Thus designed adders are verified for different supply,delay,power,leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder(MCCA),Carry Look Ahead Adder(CLAA),Carry Select Adder(CSLA),Carry Select Adder(CSA)and other adders.

New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits

New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.

Study and Evaluation in CMOS Full Adders

Low power adder circuits, SERF, 10T Ⅰ,10T Ⅱ,10T Ⅲ and a complementary adder (28T) at physical layout level are evaluated. Simulations based on the extracted adder circuit layouts are run to assess how various circuit setups can impact the speed and power consumption. In addition, impacts of output inverters on the circuit performance of modified SERF and 10T adders due to threshold loss problem are also examined. Differences among these adders are addressed and applications of these adders are suggested.

Incorporation of Reduced Full Adder and Half Adder into Wallace Multiplier and Improved Carry-Save Adder for Digital FIR Filter

Improvement of digital FIR filter is vital in the field of Digital Signal Processing in order to reduce the area, delay and power. Multiplication and Accumulation (MAC) unit of Finite Impulse Response (FIR) filter has been designed using efficient multiplier and adder circuits for optimized APT (Area,Power and Timing) product. In this paper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially, full adder and half adder structures are shrunk down by reducing number of gates. These compact full adder and half adder structures are incorporated into Wallace Multiplier and Improved Carry-Save Adder. The proposed 16-bit Carry-Save Adder has been improved by splitting into four parallel phases. Consequently the delay of enhanced Carry- Save Adder is reduced. Generation of carry output is performed using number of OR gates in a sequential manner. All these enhanced architectures are incorporated into the Digital FIR Filter to reduce the area, delay and power utilization.

Area Efficient Sparse Modulo 2n - 3 Adder

This paper presents area efficient architecture of modulo 2n - 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The proposed modulo 2n - 3 adder is implemented effectively, which utilizes parallel prefix and sparse concepts. The carries of some bits are calculated with the help of sparse approach in log2n prefix levels. This scheme is implemented with the help of idempotency property of the parallel prefix carry operator and its consistency. Parallel prefix structure contributes to fast carry computation. This will reduce area as well as routing complexity efficiently. The presented adder has double representation of residues in {0, 1, and 2}. The proposed adder offers significant reduction in area as the number of bits increases.

The Design of Ultra-Low Power Adder Cell in 90 and 180 nm CMOS Technology

In this paper, an ultra-low power adder cell is proposed. With cascading two XNOR cells, the sum of two inputs is achieved. Regarding to advantages of m-GDI XNOR cell, we constructed the adder cell based on this architecture. The simulation results show that the power consumption of the adder cell designed with GDI technology is 12.993 μw, whereas for this cell designed with m-GDI technology is 4.1628 μw, which both are designed at 0.18 um technology. Moreover, simulation results in 90 nm CMOS technology for m-GDI adder cell show average power consumption of 0.90262 μw and 6.3222 μw in 200 MHz and 2GHz, respectively.

Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics

This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.

Numerical Simulation of Azimuthal Uniformity of Injection Currents in Single-Point-Feed Induction Voltage Adders

In order to investigate the injection current uniformity around the induction cell bores, two fully electromagnetic （EM） models are respectively established for a single-stage induction cell and an induction voltage adder （IVA） with three cells stacked in series, without considering electron emission. By means of these two models, some factors affecting the injection current uni- formity are simulated and analyzed, such as the impedances of adders and loads, cell locations, and feed timing of parallel driving pulses. Simulation results indicate that higher impedances of adder and loads are slightly beneficial to improve injection current uniformity. As the impedances of adder and loads increase from 5 Ω to 30Ω, the asymmetric coefficient of feed currents decreases from 10.3% to 6.6%. The current non-uniformity within the first cell is a little worse than that in other downstream cells. Simulation results also show that the feed timing would greatly affect current waveforms, and consequently cause some distortion in pulse fronts of cell output voltages. For a given driving pulse with duration time of 70-80 ns, the feed timing with a time deviation of less than 20 ns is acceptable for the three-cell IVAs, just causing the rise time of output voltages to increase about 5 ns at most and making the peak voltage decrease by 3.5%.

A low-voltage and energy-efficient full adder cell based on carbon nanotube technology

Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET(Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP(Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.

Research of magnetic self-balance used in a repetitive high voltage rectangular waveform pulse adder

Compared with a sinusoidal operation, pulsed operation has more homogeneity and more efficiency in dielectric barrier discharge. In this paper, an improved pulse adder is designed and assembled to create repetitive high voltage rectangular pulses when resistive loads or capacitive loads exist. Beyond the normal pulse adder based on solid-state switches, additional metal- oxide-semiconductor field effect transistors are used in each stage for a faster falling edge. Further, the voltage difference between stages is eliminated by balancing windings. In this paper, we represent our theoretical derivation, software simulations and hardware experiments on magnetic self-balance. The experiments show that the voltage difference between stages is eliminated by balancing windings, which matches the result of simulations with almost identical circuits and parameters.

Designing a Full Adder Circuit Based on Quasi-Floating Gate

Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.

A Novel Design of Octal-Valued Logic Full Adder Using Light Color State Model

Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area.This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing.We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model.Four case studies were used to assure the validity of the proposed adder.These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.

A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, i.e., configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm2 and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.

Novel Adder Circuits Based On Quantum-Dot Cellular Automata (QCA)

Quantum-dot cellular automaton (QCA) is a novel nanotechnology that provides a very different computation platform than traditional CMOS, in which polarization of electrons indicates the digital information. This paper demonstrates designing combinational circuits based on quantum-dot cellular automata (QCA) nanotechnology, which offers a way to implement logic and all interconnections with only one homogeneous layer of cells. In this paper, the authors have proposed a novel design of XOR gate. This model proves designing capabilities of combinational circuits that are compatible with QCA gates within nano-scale. Novel adder circuits such as half adders, full adders, which avoid the fore, mentioned noise paths, crossovers by careful clocking organization, have been proposed. Experiment results show that the performance of proposed designs is more efficient than conventional designs. The modular layouts are verified with the freely available QCA Designer tool.

Fast Signed-Digit Multi-operand Decimal Adders

Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.

温贝尔展出冲压式喷气发动机“Adder”

1999年11月,温贝尔设计局将庆祝其建立50周年。在巴黎航展上,它展出了最新产品——远距空对空导弹R-77 AAM-AE(AA-12“蝰蛇”)的冲压式喷气发动机派生型。虽然这种派生型的外观与R-77相似,但它没有火箭发动机型上的残留弹翼,而是具有4个把空气送进导弹发动机的进气口。采用冲压发动机将显著增大导弹的射程。新型导弹还提高了抗干扰能力。 到目前为至,MIG-29的改进型和Su-27将装备冲压发动机AAM-

Bearings Intelligent Fault Diagnosis by 1-D Adder Neural Networks

Integrated with sensors,processors,and radio frequency(RF)communication modules,intelligent bearing could achieve the autonomous perception and autonomous decision-making,guarantying the safety and reliability during their use.However,because of the resource limitations of the end device,processors in the intelligent bearing are unable to carry the computational load of deep learning models like convolutional neural network(CNN),which involves a great amount of multiplicative operations.To minimize the computation cost of the conventional CNN,based on the idea of AdderNet,a 1-D adder neural network with a wide first-layer kernel(WAddNN)suitable for bearing fault diagnosis is proposed in this paper.The proposed method uses the l1-norm distance between filters and input features as the output response,thus making the whole network almost free of multiplicative operations.The whole model takes the original signal as the input,uses a wide kernel in the first adder layer to extract features and suppress the high frequency noise,and then uses two layers of small kernels for nonlinear mapping.Through experimental comparison with CNN models of the same structure,WAddNN is able to achieve a similar accuracy as CNN models with significantly reduced computational cost.The proposed model provides a new fault diagnosis method for intelligent bearings with limited resources.

Design and Test of Inductive Adder Pulse Generator for KickerMagnet

The cell circuit design and test of inductive adder pulse generator for kicker magnet are presented in the paper.The 3.3kV IGBT,a large dimension nanocrystalline core and a 2.5kV 50uF energy storage capacitor are used. The multi-channel trigger IGBT driver board is designed.IGBT failures under short circuit condition and protection scheme are explored.The multi-cell prototype is designed.The waveforms of experiments are presented.It turns out that the rise and fall time of the output pulse is fast and the pulse width is adjustable.The maximum current of pulse reaches 2kA.It satisfies the higher requirement of beam injection technology.