An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-...An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-flops are used as the storage cells and they are stacked to form the whole SRAM module. The word select bit is generated from the address decoder. And one word at a time is selected for reading or writing. The design of the memory core's layout is also discussed since it should be optimized to save area and also should be convenient for realization. It's a full-custom layout. The address decoder is composed of combinational logic circuit and its layout is also designed as a full-custom layout. With all these modules, the integral structure of the SRAM is carried out.展开更多
The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and ...The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.展开更多
文摘An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-flops are used as the storage cells and they are stacked to form the whole SRAM module. The word select bit is generated from the address decoder. And one word at a time is selected for reading or writing. The design of the memory core's layout is also discussed since it should be optimized to save area and also should be convenient for realization. It's a full-custom layout. The address decoder is composed of combinational logic circuit and its layout is also designed as a full-custom layout. With all these modules, the integral structure of the SRAM is carried out.
文摘The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.
