Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback sh...Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.展开更多
SRAM （Static RAM）-based FPGAs （Field Programmable Gate Arrays （FPGAs） have gained wide acceptance due to their on-line reconfigurable features. The growing demand for FPGAs has motivated semiconductor chip manufa...SRAM （Static RAM）-based FPGAs （Field Programmable Gate Arrays （FPGAs） have gained wide acceptance due to their on-line reconfigurable features. The growing demand for FPGAs has motivated semiconductor chip manufacturers to build more densely packed FPGAs with higher logic capacity. The downside of high density devices is that the probability of errors in such devices tends to increase. This paper proposes an FPGA architecture that is composed of an array of cells with built in error correction capability. Collectively a group of such cells can implement any logic function that is either registered or combinational. A cell is composed of three units： a logic block, a fault-tolerant address generator and a director unit. The logic block uses a look-up table to implement logic functions. The fault-tolerant address generator corrects any single bit error in the incoming data to the functional cell. The director block can transmit output data from the logic block to another cell located at its South, North, East or West, or to cells in all four directions. Thus a functional cell can also be used to route signals to other functional cells, thus avoiding any intricate network of interconnects, switching boxes, or routers commonly found in commercially available FPGAs.展开更多
基金Foundation items:Fundamental Research Funds for the Central Universities(No.JUSRP51510)Primary Research&Development Plan of Jiangsu Province(No.BE2019003-2)。
文摘Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.
基金Acknowledgement The first author was supported in part by the National Science Foundation, USA under Grant 0925080.
文摘SRAM （Static RAM）-based FPGAs （Field Programmable Gate Arrays （FPGAs） have gained wide acceptance due to their on-line reconfigurable features. The growing demand for FPGAs has motivated semiconductor chip manufacturers to build more densely packed FPGAs with higher logic capacity. The downside of high density devices is that the probability of errors in such devices tends to increase. This paper proposes an FPGA architecture that is composed of an array of cells with built in error correction capability. Collectively a group of such cells can implement any logic function that is either registered or combinational. A cell is composed of three units： a logic block, a fault-tolerant address generator and a director unit. The logic block uses a look-up table to implement logic functions. The fault-tolerant address generator corrects any single bit error in the incoming data to the functional cell. The director block can transmit output data from the logic block to another cell located at its South, North, East or West, or to cells in all four directions. Thus a functional cell can also be used to route signals to other functional cells, thus avoiding any intricate network of interconnects, switching boxes, or routers commonly found in commercially available FPGAs.
