DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

Design of ternary low-power Domino JKL flip-flop and its application

By researching the ternary flip-tlop and the adiabatic Domino circuit,a novel design of low-power ternary Domino JKL flip-flop on the switch level is proposed.First,the switch-level structure of the ternary adiabatic Domino JKL flip-flop is derived according to the switch-signal theory and its truth table.Then the ternary loop operation circuit and ternary reverse loop operation circuit are achieved by employing the ternary JKL tlip-tlop. Finally,the circuit is simulated by using the Spice tool and the results show that the logic function is correct. The energy consumption of the ternary adiabatic Domino JKL flip-flop is 69%less than its conventional Domino counterpart.