We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect（SHE） in 14 nm bulk n Fin FETs with ambient temperature（TA） from 220 to 400 K. Based on this method, nonloca...We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect（SHE） in 14 nm bulk n Fin FETs with ambient temperature（TA） from 220 to 400 K. Based on this method, nonlocal heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/Si O_2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below：（i） not all input power（Q_（input） turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport;（ii） a higher TA leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages;（iii） SHE can lead to serious degradation in the carrier transport, which will increase when TA increases;（iv） the current degradation can be 8.9% when Vds = 0.7 V, Vgs = 1 V and TA = 400 K;（v） device thermal resistance（Rth） increases with increasing of TA, which is seriously impacted by the non-equilibrium transport. Hence, the impact of TA should be carefully considered when investigating SHE in nanoscale devices.展开更多
基金supported by the National Key Technology Research and Development Program of China(No.2016YFA0202101)the National Natural Science Foundation of China(Nos.61421005,61604005)+1 种基金the National High-Tech R&D Program(863 Program)(No.2015AA016501)The simulation was carried out at National Supercomputer Center in Tianjin,with Tian He-1(A)
文摘We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect（SHE） in 14 nm bulk n Fin FETs with ambient temperature（TA） from 220 to 400 K. Based on this method, nonlocal heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/Si O_2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below：（i） not all input power（Q_（input） turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport;（ii） a higher TA leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages;（iii） SHE can lead to serious degradation in the carrier transport, which will increase when TA increases;（iv） the current degradation can be 8.9% when Vds = 0.7 V, Vgs = 1 V and TA = 400 K;（v） device thermal resistance（Rth） increases with increasing of TA, which is seriously impacted by the non-equilibrium transport. Hence, the impact of TA should be carefully considered when investigating SHE in nanoscale devices.
