Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout a...Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout automation,analog IC layout design is still heavily manual,which leads to a more time-consuming and error-prone process.In recent years,significant progress has been made in automated analog layout design with emerging of several open-source frameworks.This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges.We then present recent research trends and opportunities in the field.Finally,we summaries the paper with open questions and future directions for fully-automating the analog IC layout.展开更多
Our contention is that reality is actually analog, but at a critical limit, when the Octonian gravity condition kicks in, for a time it is made to appear discrete. This is due to an initial phase transition just at th...Our contention is that reality is actually analog, but at a critical limit, when the Octonian gravity condition kicks in, for a time it is made to appear discrete. This is due to an initial phase transition just at the start of the big bang. Our second consideration is that symmetry breaking models, i.e. the Higgs boson, are in themselves not appropriate or necessary for the formation of particles with mass just before Octonionic gravity which could arise in pre-Planckian physics models without a potential. Finally, the necessity of potentials for pre-Octonionic gravity physics can be circumvented via judicious use of Scherrer k essence physics.展开更多
单对线以太网是近年来新兴的以太网技术,随着汽车自动驾驶和工业物联网的高速发展,凭借上层应用扩展和底层布线上的绝对优势,正在大规模应用。单对线以太网物理层模拟前端技术是实现单对线以太网通信的关键基础技术。本文讲述了现有单...单对线以太网是近年来新兴的以太网技术,随着汽车自动驾驶和工业物联网的高速发展,凭借上层应用扩展和底层布线上的绝对优势,正在大规模应用。单对线以太网物理层模拟前端技术是实现单对线以太网通信的关键基础技术。本文讲述了现有单对线以太网物理层模拟前端相关的标准,架构及相关模块设计技术,重点对发射器TX和接收器RX关键模块的现有实现技术及其优缺点进行了列举分析。发射器TX电流模结构易于实现高精度但功耗效率低,电压模结构精度略低但功耗效率更高;接收器RX的设计围绕模拟数字转换器(Analog-to-Digital Converter,ADC)展开,ADC决定着整个RX的性能、功耗、面积和复杂度,分段和重新装配(Segmentation And Reassembly,SAR)ADC是首选结构,应用上限不断提高。由此进一步明确了在高性能、低功耗、小面积的单对线以太网物理层模拟前端设计中的挑战。展开更多
There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon...There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.展开更多
目的分析视觉模拟评估法(visual analog scale,VAS)应用于慢性阻塞性肺疾病急性加重期(AECOPD)患者症状感知的实用性及其影响因素。方法通过对2021年2月至2021年8月在阜阳市人民医院住院诊治的455例AECOPD患者的不同症状表型(咳嗽、咳...目的分析视觉模拟评估法(visual analog scale,VAS)应用于慢性阻塞性肺疾病急性加重期(AECOPD)患者症状感知的实用性及其影响因素。方法通过对2021年2月至2021年8月在阜阳市人民医院住院诊治的455例AECOPD患者的不同症状表型(咳嗽、咳痰、喘息、乏力)进行VAS评分,分析其与多种评分之间的相关性;并采用多元线性回归进一步寻找其影响因素。结果VAS((总))评定简单、迅速、有效,与CAT、CPIS、BODE指数和HAD评分结果均高度相关,与各表型VAS之间亦有着一定的相关性;其中,患者近1年急性加重次数、感染、分泌物性状、FEV1%pred、抑郁、焦虑均是VAS((总))的影响因素。结论临床上可尝试采用VAS评分对患者进行高效评定,其中病患情绪因素也需要引起重视。展开更多
基金supported in part by the NSF under Grant No.1704758,and the DARPA IDEA program.
文摘Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout automation,analog IC layout design is still heavily manual,which leads to a more time-consuming and error-prone process.In recent years,significant progress has been made in automated analog layout design with emerging of several open-source frameworks.This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges.We then present recent research trends and opportunities in the field.Finally,we summaries the paper with open questions and future directions for fully-automating the analog IC layout.
文摘Our contention is that reality is actually analog, but at a critical limit, when the Octonian gravity condition kicks in, for a time it is made to appear discrete. This is due to an initial phase transition just at the start of the big bang. Our second consideration is that symmetry breaking models, i.e. the Higgs boson, are in themselves not appropriate or necessary for the formation of particles with mass just before Octonionic gravity which could arise in pre-Planckian physics models without a potential. Finally, the necessity of potentials for pre-Octonionic gravity physics can be circumvented via judicious use of Scherrer k essence physics.
文摘单对线以太网是近年来新兴的以太网技术,随着汽车自动驾驶和工业物联网的高速发展,凭借上层应用扩展和底层布线上的绝对优势,正在大规模应用。单对线以太网物理层模拟前端技术是实现单对线以太网通信的关键基础技术。本文讲述了现有单对线以太网物理层模拟前端相关的标准,架构及相关模块设计技术,重点对发射器TX和接收器RX关键模块的现有实现技术及其优缺点进行了列举分析。发射器TX电流模结构易于实现高精度但功耗效率低,电压模结构精度略低但功耗效率更高;接收器RX的设计围绕模拟数字转换器(Analog-to-Digital Converter,ADC)展开,ADC决定着整个RX的性能、功耗、面积和复杂度,分段和重新装配(Segmentation And Reassembly,SAR)ADC是首选结构,应用上限不断提高。由此进一步明确了在高性能、低功耗、小面积的单对线以太网物理层模拟前端设计中的挑战。
基金supported in part by the National Natural Science Foundation of China(Nos.12005245,12075100,and 11775244)by the Scientific and Technological Innovation Project(No.2020000165)from the Institute of High Energy Physics,Chinese Academy of Sciences+1 种基金partially funded by the Scientific Instrument Development Project of the Chinese Academy of Sciences(No.ZDKYYQ20200007)Youth Innovation Promotion Association of the Chinese Academy of Sciences(No.Y201905).
文摘There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.
文摘目的分析视觉模拟评估法(visual analog scale,VAS)应用于慢性阻塞性肺疾病急性加重期(AECOPD)患者症状感知的实用性及其影响因素。方法通过对2021年2月至2021年8月在阜阳市人民医院住院诊治的455例AECOPD患者的不同症状表型(咳嗽、咳痰、喘息、乏力)进行VAS评分,分析其与多种评分之间的相关性;并采用多元线性回归进一步寻找其影响因素。结果VAS((总))评定简单、迅速、有效,与CAT、CPIS、BODE指数和HAD评分结果均高度相关,与各表型VAS之间亦有着一定的相关性;其中,患者近1年急性加重次数、感染、分泌物性状、FEV1%pred、抑郁、焦虑均是VAS((总))的影响因素。结论临床上可尝试采用VAS评分对患者进行高效评定,其中病患情绪因素也需要引起重视。
