A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Simulation and Design Optimization of Novel Microelectromechanical Digital-to-Analog Converter

A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary voltage to the output of analog displacement,the gaps are proposed to be employed as a scale factor.A finite element method is used to simulate the performance of the DAC.To reduce the error,the structure design is optimized and the maximum error of 0 002μm is obtained.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

Design of Digital to Analog Converters with Arbitrary Radix

There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.

Analog-to-digital conversion of information in the retina

We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.

一种应用于12 bit SAR ADC C-R混和式DAC

针对ADC中功耗、精度与成本之间相互制约的问题,提出一种应用于12 bitSARADC的混合电容电阻型(C-R)DAC结构。高6位采用温度计编码的电容阵列结构;低6位选择电阻阵列结构。对电路进行非线性分析选取合理的元件尺寸。另外,采用非交叠时钟电路作为开关控制时序,避免开关切换时引起瞬态毛刺导致电容电荷泄露。基于GSMC 95 nm工艺,完成电路、版图设计与仿真,并完成流片测试,DAC版图总面积为317.2μm×262.5μm,流片测试结果表明,DNL的范围为-0.38~+0.44 LSB,INL的范围为-0.73~+0.4 LSB,满足12位ADC的设计要求。

基于VHDL-AMS的模数转换器辐射效应建模与仿真方法

模数转换器(Analog-to-Digital Converter,ADC)是连接模拟信号域与数字信号域的关键器件,而现有研究缺乏ADC辐照效应建模的相关内容.为满足大型模数混合信号系统辐照效应建模仿真的需要,本文提出了建立具有辐照效应的ADC行为级模型的方法.首先根据ADC的工作原理将其拆解为不同的通用模块,使用模拟和混合信号硬件描述语言(Very High speed integrated circuit hardware Description Language for Analog and Mixed Signals,VHDL-AMS)建立了各模块的行为级模型.接着根据基本原理将各模块动态组合为未辐照情况下基本的ADC模型.对于ADC的辐照效应,通过开展辐照试验,测量了ADC芯片HWD7710和SAD9434受总剂量(Total Ionizing Dose,TID)效应和中子辐射(Neutron Radiation,NR)效应影响的工作参数,并利用最小二乘法拟合获得ADC的工作参数与辐照剂量的关系式.最后根据辐照关系式,在基本模型上添加辐照参数模块,并建立两种不同结构ADC的TID与NR模型.通过仿真结果与试验数据对比,验证了所建ADC辐射效应模型的普适性和精度.模型的静态参数仿真结果与试验结果的相对偏差在5%以内,证明该方法支持对不同ADC及不同辐射效应进行辐照效应模型建模.

基于MCS-51的高精度信号发生器设计与仿真验证

本文设计的信号发生器以MCS-51单片机为核心,辅助以按键电路、显示电路、数模转换电路,能够发出三角波、正弦波、方波、锯齿波四种波形。通过引入DAC0823芯片,将数字量和模拟量进行转换,使得信号发生器发出的波形的误差和噪声干扰更小,并简化了滤波过程。仿真过程中通过软件程序控制硬件电路,利用Keil仿真平台的元器件仿真功能和程序编辑功能将程序搭建好,然后一同放入Proteus仿真平台中,通过后者的元器件选择和参数调节功能将信号发生器的主控电路搭建完成。最后,利用模拟示波器得到了满足设计要求的波形,验证了信号发生器的性能。

Ionizing radiation effect on 10-bit bipolar A/D converter

In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias and dose rate. Under high-dose-rate irradiation,the ADC functions well,while under low-dose-rate irradiation,the parameters of ADC change obviously at low dose level,and the damage is significant at zero bias.Combining the fringing field with the space charge model,the underlying mechanism for this response is discussed.

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

A 12-bit 250-MS/s Charge-Domain Pipelined Analog-to-Digital Converter with Feed-Forward Common-Mode Charge Control

A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.

工艺-电压-温度综合稳健的亚1 V 10位SAR ADC

采用0.11-μm CMOS工艺设计了一款10位亚1 V工艺-电压-温度(Process-Voltage-Temperature,PVT)综合稳健的逐次逼近寄存器型(Successive-Approximation-Register,SAR)模数转换器(Analog-to-Digital Converter,ADC)IP核.由于SAR ADC数字化程度较高,为了降低整体功耗,采用小于标准电压的亚1 V供电.然而,对于异步SAR ADC,在低压下面临严峻的PVT不稳健问题,传统采用固定延迟电路的方式无法应对所有的PVT偏差,会导致ADC良率下降.提出一种用于异步SAR ADC的可配置延迟调控技术,采用3输入译码器调节延迟电路的电流,以满足ADC在多种PVT组合下所需的延时,在TT,SS,FF,SF,FS这5种工艺角,0.9~1 V供电范围和-40~85℃的温度范围下,均取得了良好的动态特性.在0.95 V供电,采样速率为200 kS/s时,总功耗为2.24μW,FoM值仅为16.46 fJ/Conv.-step.

An ultra high-speed 8-bit timing interleave folding＆interpolating analog-to-digital converter with digital foreground calibration technology

A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.

The total ionizing dose effect in 12-bit, 125 MSPS analog-to-digital converters

This paper presents the total ionizing dose test results at different biases and dose rates for AD9233, which is fabricated using a modern CMOS process. The experimental results show that the digital parts are more sensitive than the other parts. Power down is the worst-case bias, and this phenomenon is first found in the total ionizing dose effect of analog-to-digital converters. We also find that the AC as well as DC parameters are sensitive to the total ionizing dose at a high dose rate, whereas none of the parameters are sensitive at a low dose rate. The test facilities, results and analysis are presented in detail.

A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB ＆ INL less than ±4.3 LSB after the chip is calibrated.

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.

A FAST FOREGROUND DIGITAL CALIBRATION TECHNIQUE FOR PIPELINED ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.