Due to variable time for charge collection,energy resolution of nuclear detectors declines,especially compound semiconductor detectors like cadmium zinc telluride(CdZnTe) detector.To solve this problem,an analog rise-...Due to variable time for charge collection,energy resolution of nuclear detectors declines,especially compound semiconductor detectors like cadmium zinc telluride(CdZnTe) detector.To solve this problem,an analog rise-time discriminator based on charge comparison principle is designed.The reference charge signal after attenuation is compared with the deconvoluted and delayed current signal.It is found that the amplitude of delayed current signal is higher than that of the reference charge signal when rise time of the input signal is shorter than the discrimination time,thus generating gating signal and triggering DMCA(digital multi-channel analyzer) to receive the total integral charge signal.When rise time of the input signal is longer than discrimination time,DMCA remains inactivated and the corresponding total integral charge signal is abandoned.Test results show that combination of the designed rise-time discriminator and DMCA can reduce hole tailing of CdZnTe detector significantly.Energy resolution of the system is 0.98%@662 keV,and it is still excellent under high counting rates.展开更多
We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg gratin...We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg grating is optimally designed and used to compensate for the entire time-delays of the quantized pulses precisely. Simulation results show that the compensated coding pulses are well synchronized with a time difference less than 3.3 ps, which can support a maximum sampling rate of 151.52 GSa/s. The proposed scheme can efficiently reduce the structure complexity and cost of all-optical analog-to-digital conversion compared to the previous schemes with multiple optical time-delay lines.展开更多
A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital c...A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.展开更多
An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integra...An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift （SSFS） module within a wavelength range of 1550 nm-1580 nm. A dispersion coefficient as high as -19800 ps/（km.nm） with ＋0.5 ps/（km.nm） variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate （MSSR） is 50.45 GSa/s with full width at half maximum （FWHM） variation less than 2.52 ps, along with the 2-bit effective- number-of-bit and Gray code output.展开更多
This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the...This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.展开更多
A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels ...A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.展开更多
随着雷达信号处理技术的发展,对于宽带线性调频(Linear Frequency Modulation)信号发生器的需求也变得十分迫切。基于Xilinx公司的直接数字频率合成(Direct Digital frequency Synthesis,DDS)IP核和高速数模转换器(Digital-to-Analog Co...随着雷达信号处理技术的发展,对于宽带线性调频(Linear Frequency Modulation)信号发生器的需求也变得十分迫切。基于Xilinx公司的直接数字频率合成(Direct Digital frequency Synthesis,DDS)IP核和高速数模转换器(Digital-to-Analog Converter,DAC)的架构,设计了一种可实时切换参数的多相宽带线性调频信号发生器,并完成仿真和上板验证。经仿真和上板验证,该信号发生器能够根据任务要求实时切换线性调频信号的参数,生成的信号指标准确,实现方法可靠,具有一定的实用价值。展开更多
基金supported by the Natural Science Foundation of China(NSFC)(No.41474159)National High-tech R&D Program of China(863 Program)(Nos.2012AA061803 and 2014AA093403)Open Foundation of Applied Nuclear Techniques in Geosciences Key Laboratory of Sichuan Province(No.gnzds2014006)
文摘Due to variable time for charge collection,energy resolution of nuclear detectors declines,especially compound semiconductor detectors like cadmium zinc telluride(CdZnTe) detector.To solve this problem,an analog rise-time discriminator based on charge comparison principle is designed.The reference charge signal after attenuation is compared with the deconvoluted and delayed current signal.It is found that the amplitude of delayed current signal is higher than that of the reference charge signal when rise time of the input signal is shorter than the discrimination time,thus generating gating signal and triggering DMCA(digital multi-channel analyzer) to receive the total integral charge signal.When rise time of the input signal is longer than discrimination time,DMCA remains inactivated and the corresponding total integral charge signal is abandoned.Test results show that combination of the designed rise-time discriminator and DMCA can reduce hole tailing of CdZnTe detector significantly.Energy resolution of the system is 0.98%@662 keV,and it is still excellent under high counting rates.
基金Project supported by the National Basic Research Program,China(Grant Nos.2010CB327605 and 2010CB328300)the National High-Technology Research and Development Program of China(Grant No.2013AA031501)+7 种基金the National Natural Science Foundation of China(Grant No.61307109)the Specialized Research Fund for the Doctoral Program of Higher Education of China(Grant No.20120005120021)the Fundamental Research Funds for the Central Universities,China(Grant No.2013RC1202)the Program for New Century Excellent Talents in University,China(Grant No.NECT-11-0596)the Beijing Nova Program,China(Grant No.2011066)the Fund of State Key Laboratory of Information Photonics and Optical Communications(Beijing University of Posts and Telecommunications) Chinathe China Postdoctoral Science Foundation(Grant No.2012M511826)the Postdoctoral Science Foundation of Guangdong Province,China(Grant No.244331)
文摘We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg grating is optimally designed and used to compensate for the entire time-delays of the quantized pulses precisely. Simulation results show that the compensated coding pulses are well synchronized with a time difference less than 3.3 ps, which can support a maximum sampling rate of 151.52 GSa/s. The proposed scheme can efficiently reduce the structure complexity and cost of all-optical analog-to-digital conversion compared to the previous schemes with multiple optical time-delay lines.
文摘A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.
基金supported by the Fundamental Research Funds for the Central Universities,China(Grant No.FRF-TP-15-030A1)China Postdoctoral Science Foundation(Grant No.2015M580978)
文摘An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift （SSFS） module within a wavelength range of 1550 nm-1580 nm. A dispersion coefficient as high as -19800 ps/（km.nm） with ＋0.5 ps/（km.nm） variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate （MSSR） is 50.45 GSa/s with full width at half maximum （FWHM） variation less than 2.52 ps, along with the 2-bit effective- number-of-bit and Gray code output.
文摘This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.
基金Supported by the National Natural Science Foundation of China (No. 61076026)
文摘A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.
文摘随着雷达信号处理技术的发展,对于宽带线性调频(Linear Frequency Modulation)信号发生器的需求也变得十分迫切。基于Xilinx公司的直接数字频率合成(Direct Digital frequency Synthesis,DDS)IP核和高速数模转换器(Digital-to-Analog Converter,DAC)的架构,设计了一种可实时切换参数的多相宽带线性调频信号发生器,并完成仿真和上板验证。经仿真和上板验证,该信号发生器能够根据任务要求实时切换线性调频信号的参数,生成的信号指标准确,实现方法可靠,具有一定的实用价值。
