An Adaptive Control Strategy for Energy Storage Interface Converter Based on Analogous Virtual Synchronous Generator

In the DC microgrid,the lack of inertia and damping in power electronic converters results in poor stability of DC bus voltage and low inertia of the DC microgrid during fluctuations in load and photovoltaic power.To address this issue,the application of a virtual synchronous generator(VSG)in grid-connected inverters control is referenced and proposes a control strategy called the analogous virtual synchronous generator(AVSG)control strategy for the interface DC/DC converter of the battery in the microgrid.Besides,a flexible parameter adaptive control method is introduced to further enhance the inertial behavior of the AVSG control.Firstly,a theoretical analysis is conducted on the various components of the DC microgrid,the structure of analogous virtual synchronous generator,and the control structure’s main parameters related to the DC microgrid’s inertial behavior.Secondly,the voltage change rate tracking coefficient is introduced to adjust the change of the virtual capacitance and damping coefficient flexibility,which further strengthens the inertia trend of the DC microgrid.Additionally,a small-signal modeling approach is used to analyze the approximate range of the AVSG’s main parameters ensuring system stability.Finally,conduct a simulation analysis by building the model of the DC microgrid system with photovoltaic(PV)and battery energy storage(BES)in MATLAB/Simulink.Simulation results from different scenarios have verified that the AVSG control introduces fixed inertia and damping into the droop control of the battery,resulting in a certain level of inertia enhancement.Furthermore,the additional adaptive control strategy built upon the AVSG control provides better and flexible inertial support for the DC microgrid,further enhances the stability of the DC bus voltage,and has a more positive impact on the battery performance.

A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Simulation and Design Optimization of Novel Microelectromechanical Digital-to-Analog Converter

A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary voltage to the output of analog displacement,the gaps are proposed to be employed as a scale factor.A finite element method is used to simulate the performance of the DAC.To reduce the error,the structure design is optimized and the maximum error of 0 002μm is obtained.

A Design of High-precision High-Voltage Fiber-Optic Analog Signal Isolation Converter

This paper introduces a design of high-precision high-voltage fiber-optic analog sig-nal isolation converter based on the technology of Voltage-to-Frequency (V/F) and Frequency-to-Voltage (F/V) conversion. It describes the principle, system configuration and hardware design.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

Design of Digital to Analog Converters with Arbitrary Radix

There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

A Low-Power 12-Bit SAR ADC for Analog Convolutional Kernel of Mixed-Signal CNN Accelerator

As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.

200Ms/s 177mW 8bit Folding and Interpolating CMOS A/D Converter

A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.

Ionizing radiation effect on 10-bit bipolar A/D converter

In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias and dose rate. Under high-dose-rate irradiation,the ADC functions well,while under low-dose-rate irradiation,the parameters of ADC change obviously at low dose level,and the damage is significant at zero bias.Combining the fringing field with the space charge model,the underlying mechanism for this response is discussed.

Analog-to-digital conversion of information in the retina

We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.

基于Analog Discovery 2的电机解码系统设计

介绍了一种适用于高性能电机转子位置解码系统的设计方案。在阐明旋变基本工作原理的基础上,给出了该系统的详细设计思路及参数选择。重点介绍了围绕Analog Discovery 2芯片的外围电路、激励驱动电路以及与TC1782的接口电路。

基于0.18μm SiGe BiCMOS工艺的4GS/s、14 bit数模转换器

基于0.18μm SiGe BiCMOS工艺,设计了超高速高精度数模转换器(DAC),其时钟采样率为4 GS/s、精度为14 bit。为满足4 GHz处理速度,该DAC中所有电路均采用异质结晶体管(HBTs)搭建。为了降低功耗和节约面积,本设计采用10+4分段译码的方式,其中低10位电流舵使用R-2R梯形电阻网络,而高4位使用温度计码结构。仿真结果表明,所设计DAC的DNL、INL分别为0.54 LSB和0.39 LSB,全奈奎斯特频域内的无杂散动态范围均大于82 dBc。在3.3 V和5 V混合电源供电下,整个DAC的平均功耗为2.39 W。芯片总面积为11.22 mm^(2)。

一种应用于12 bit SAR ADC C-R混和式DAC

针对ADC中功耗、精度与成本之间相互制约的问题,提出一种应用于12 bitSARADC的混合电容电阻型(C-R)DAC结构。高6位采用温度计编码的电容阵列结构;低6位选择电阻阵列结构。对电路进行非线性分析选取合理的元件尺寸。另外,采用非交叠时钟电路作为开关控制时序,避免开关切换时引起瞬态毛刺导致电容电荷泄露。基于GSMC 95 nm工艺,完成电路、版图设计与仿真,并完成流片测试,DAC版图总面积为317.2μm×262.5μm,流片测试结果表明,DNL的范围为-0.38~+0.44 LSB,INL的范围为-0.73~+0.4 LSB,满足12位ADC的设计要求。

一种基于冗余位结构CDAC的12 bit SAR ADC

提出一种基于非二进制冗余位结构CDAC的12 bit全差分逐次逼近型模拟数字转换器(SAR ADC)。传统SAR ADC中CDAC的单位电容数量随位数指数增长,且采用全差分结构的电容数量是单端结构的两倍,导致CDAC建立时间过长。为此,设计一种加入冗余位的分段式电容阵列,减少单位电容数量,提高CDAC建立速度。动态比较器的比较速度快,会导致数字码误判,通过加入冗余位弥补比较器对数字码误判的缺陷;采用底板采样技术,避免沟道电荷注入和时钟馈通,提高采样精度;采用SMIC 130 nm CMOS工艺。在电源电压1.2 V、20 MS/s采样率下,对1024点FFT仿真。结果显示:当输入频率(9.824 MHz)接近奈奎斯特频率时,该ADC的整体信噪失真比(SNDR)达到72.42 dB,有效位数(ENOB)达到11.73 bit;无杂散动态范围(SFDR)达到88.4 dBc,功耗为1.29 mW。

基于量子电压的模数转换器性能评估

相比于用传统半导体器件研制的信号源,约瑟夫森任意波形发生器合成信号的幅值可溯源至自然常数,其输出波形具有超低噪声、超低失真的优点。使用约瑟夫森任意波形发生器评估了National Instruments公司24位数字采集卡PXI 5922的性能。其中,采用零补偿波形合成方法简化系统硬件结构,并且使用高精度、多比例的感应分压器提升评估效率。首先,在10 kHz的带宽内标定了PXI 5922单通道的增益及其稳定性、信噪比、无杂散动态范围、总谐波失真、信纳比和有效位数;其次,标定了PXI 5922两通道不同相位下的相位差;最后,结合电网的谐波情况,以60 Hz的基波频率为例,标定了PXI 5922在12阶谐波以内各谐波的幅度与相位响应。约瑟夫森任意波形发生器的超高精度和宽带输出能力在评估高精度模数转换器的性能方面具有广阔的应用前景。

一种16位110 dB无杂散动态范围的低功耗SAR ADC

该文设计了一款16位、转换速率为625 kS/s的逐次逼近寄存器型模数转换器(SAR ADC)。改进的采样保持电路结构,优化了采样线性度和噪声性能。采用分段结构设计电容型数模转换器并使用混合方式的电容切换方案,减小面积和能耗。利用扰动注入技术提升ADC的线性度。比较器采用两级积分型预放大器减小噪声,利用输出失调存储技术及优化的电路设计减小了比较器失调电压和失调校准引入的噪声,优化并提升了比较器速度。芯片采用CMOS 0.18μm工艺设计和流片,ADC核心面积为1.15 mm^(2)。测试结果表明,在1 kHz正弦信号输入下,ADC差分输入峰峰值幅度达8.8 V,信纳比为85.9 dB,无杂散动态范围为110 dB,微分非线性为-0.27/+0.32 LSB,积分非线性为-0.58/+0.53 LSB,功耗为4.31 mW。

一种6倍无源增益低OSR低功耗的二阶NS SAR ADC

针对一阶噪声整形(NS)往往需要增加功耗而以较高的过采样比(OSR)来实现较高的有效位数(ENOB),提出了一种低OSR、低功耗的二阶无源NS SAR ADC。该无源NS模块较高的无源增益可以更好地抑制比较器的噪声;其残差电压是通过开关MOS阵列复用积分电容实现采样,从而无需额外的残差采样电容,避免了残差采样电容清零和残差采样时kT/C噪声的产生,因此减小了总的kT/C噪声。180 nm CMOS工艺仿真结果表明,在不使用数字校准的情况下,所设计的10位二阶无源NS SAR ADC电路以100 kS/s的采样率和5的OSR,实现了13.5位ENOB,电路功耗仅为6.98μW。