Type Synthesis of Self-Alignment Parallel Ankle Rehabilitation Robot with Suitable Passive Degrees of Freedom

The current parallel ankle rehabilitation robot(ARR)suffers from the problem of difficult real-time alignment of the human-robot joint center of rotation,which may lead to secondary injuries to the patient.This study investigates type synthesis of a parallel self-alignment ankle rehabilitation robot(PSAARR)based on the kinematic characteristics of ankle joint rotation center drift from the perspective of introducing"suitable passive degrees of freedom(DOF)"with a suitable number and form.First,the self-alignment principle of parallel ARR was proposed by deriving conditions for transforming a human-robot closed chain(HRCC)formed by an ARR and human body into a kinematic suitable constrained system and introducing conditions of"decoupled"and"less limb".Second,the relationship between the self-alignment principle and actuation wrenches(twists)of PSAARR was analyzed with the velocity Jacobian matrix as a"bridge".Subsequently,the type synthesis conditions of PSAARR were proposed.Third,a PSAARR synthesis method was proposed based on the screw theory and type of PSAARR synthesis conducted.Finally,an HRCC kinematic model was established to verify the self-alignment capability of the PSAARR.In this study,93 types of PSAARR limb structures were synthesized and the self-alignment capability of a human-robot joint axis was verified through kinematic analysis,which provides a theoretical basis for the design of such an ARR.

Self-alignment of full skewed RSINS: observability analysis and full-observable Kalman filter

Traditional orthogonal strapdown inertial navigation sys-tem （SINS） cannot achieve satisfactory self-alignment accuracy in the stationary base： taking more than 5 minutes and al the iner-tial sensors biases cannot get ful observability except the up-axis accelerometer. However, the ful skewed redundant SINS （RSINS） can not only enhance the reliability of the system, but also improve the accuracy of the system, such as the initial alignment. Firstly, the observability of the system state includes attitude errors and al the inertial sensors biases are analyzed with the global perspective method： any three gyroscopes and three accelerometers can be assembled into an independent subordinate SINS （sub-SINS）;the system state can be uniquely confirmed by the coupling connec-tions of al the sub-SINSs;the attitude errors and random constant biases of al the inertial sensors are observable. However, the ran-dom noises of the inertial sensors are not taken into account in the above analyzing process. Secondly, the ful-observable Kalman filter which can be applied to the actual RSINS containing random noises is established; the system state includes the position, ve-locity, attitude errors of al the sub-SINSs and the random constant biases of the redundant inertial sensors. At last, the initial self-alignment process of a typical four-redundancy ful skewed RSINS is simulated： the horizontal attitudes （pitch, rol ） errors and yaw error can be exactly evaluated within 80 s and 100 s respectively, while the random constant biases of gyroscopes and accelero-meters can be precisely evaluated within 120 s. For the ful skewed RSINS, the self-alignment accuracy is greatly improved, mean-while the self-alignment time is widely shortened.

Scalable fabrication of geometry-tunable self-aligned superlattice photonic crystals for spectrum-programmable light trapping

Superlattice photonic crystals (SPhCs) possess considerablepotentials as building blocks for constructing high-performancedevices because of their great flexibilities in opticalmanipulation. From the prospective of practical applications,scalable fabrication of SPhCs with large-area uniformity and precisegeometrical controllability has been considered as one prerequisitebut still remains a challenge.

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering （DIBL） was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET, These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.

Self-Aligned Titanium Silicide NMOS and 12-Bit Multiplier

Self-aligned Titanium Silicide (Salicide), Light-Doped Drain (LDD) technology was studied. Results show that, this technology suppresses effectivily short-channel effects. The sheet resistance of active region decreases by four times. The sheet resistance of polysilicon gate region decreases by one order of magnitute. Using this technology, the speed of the 3 μm NMOS 12-bits multiplier increases by two times relative to conventional one.

Excellent-Performance AlGaN/GaN Fin-MOSHEMTs with Self-Aligned Al_2O_3Gate Dielectric

A1GaN/GaN fin-shaped metal-oxide-semiconductor high-electron-mobility transistors （fin-MOSHEMTs） with dif- ferent fin widths （30Ohm and lOOnm） on sapphire substrates are fabricated and characterized. High-quality self-Migned Al2O3 gate dielectric underneath an 80-nm T-shaped gate is employed by Muminum self-oxidation, which induces 4 orders of magnitude reduction in the gate leakage current. Compared with conventional planar MOSHEMTs, short channel effects of the fabricated fin-MOSHEMTs are significantly suppressed due to the tri- gate structure, and excellent de characteristics are obtained, such as extremely fiat output curves, smaller drain induced barrier lower, smaller subthreshold swing, more positive threshold voltage, higher transconductance and higher breakdown voltage.

Innovation on Line Cut Methods of Self-aligned Multiple Patterning

Self-aligned multiple patterning (SAMP) can enable the semiconductor scaling before EUV lithography becomes mature for industry use.Theoretically any small size of pitch can be achieved by repeating SADP on same wafer but with challenges of pitch walking and line cut since line cut has to be done by lithography instead of self-aligned method.Line cut can become an issue at sub-30nm pitch due to edge placement error (EPE).In this paper we will discuss some recent novel ideas on line cut after self-aligned multiple patterning.

A Photolithography Process Design for 5 nm Logic Process Flow

With the introduction of EUV lithography,the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method.In a typical 5 nm logic process,the contact-poly pitch(CPP)is 44-50 nm,the minimum metal pitch(MPP)is around 30-32 nm.And the overlay budget is estimated to be 2.5 nm(on product overlay).Although the optical resolution of a 0.33NA exposure tool(such as ASML NXE3400)can reach below 32 nm pitch,stochastics in the EUV absorption in photoresists has limited its application to smaller pitches.For the CPP mentioned above,one can use 193 nm immersion lithography with Self-Aligned Double Patterning(SADP)technique to provide good image contrast(or CDU,LWR)as well as good overlay,as for the 10 and 7 nm generations.In the BEOL,however,the 30-32 pitch cannot be realized by a single EUV exposure with enough printing defect process window.If this pitch is to be done by 193 nm immersion lithography,more than 6-8 exposures are needed with very complicated overlay result.For EUV,this can be done through self-aligned LELE with both good CD and overlay control.We have done an optimization of the photolithographic process parameters for the typical metal with a self-developed aerial image simulator based on rigorous coupled wave analysis(RCWA)algorithm and the Abbe imaging routine with an EUV absorption model which describes stochastics.We have calibrated our model with wafer exposure data from several photoresists under collaboration with IMEC.As we have presented last year,to accommodate all pitches under a logic design rule,as well as to provide enough CDU for the logic device performance,in DUV lithography,a typical minimum exposure latitude(EL)for the poly and metal layers can be set at,respectively,18%and 13%.In EUV,due to the existence of stochastics,13%EL,which corresponds to an imaging contrast of 40%,seems not enough for the metal trenches,and to obtain an imaging contrast close to 100%,which yields an EL of 31.4%means that we need to relax minimum pitch to above 41 nm(conventional imaging limit for 0.33NA).This is the best imaging contrast a photolithographic process can provide to reduce LWR and stochastics.In EUV,due to the significantly smaller numerical apertures compared to DUV,the aberration impact can cause much more pronounced image registration error,in order to satisfy 2.5 nm total overlay,the aberration induced shift needs to be kept under 0.2 nm.We have also studied shadowing effect and mask 3D scattering effect and our results will be provided for discussion.

Improvement of Interfacial Adhesion Strength and Thermal Stability of Cu/p-SiC:H/SiOC:H Film Stack by Plasma Treatment on the Surface of Cu Film

A highly reliable interface of self-aligned barrier CuSiN thin layer between the Cu film and the nano-porous SiC：H （p-SiC：H） capping barrier （k=3.3） has been developed in the present work. With the introduction of self-aligned barrier （SAB） CuSiN between a Cu film and a p-SiC：H capping barrier, the interfacial thermal stability and the adhesion of the Cu/p-SiC：H film are considerably enhanced. A significant improvement of adhesion strength and thermal stability of Cu/p-SiC：H/SiOC：H film stack has been achieved by optimizing the pre-clean step before caplayer deposition and by forming the CuSiN-like phase. This cap layer on the surface of the Cu can provide a more cohesive interface and effectively suppress Cu atom migration as well.

Key Process Approach Recommendation for 5 nm Logic Process Flow with EUV Photolithography

5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries.In a typical 5 nm logic process,the Fin pitch is 22~27 nm,the contact-poly pitch(CPP)is 48?55 nm,and the minimum metal pitch(MPP)is around 30~36 nm.Due to the fact that these pitches are much smaller than the resolution capability of 193 nm immersion lithography,it is also the first generation which adopts EUV photolithography technology on a large-scale where the process flow can be simplified by single exposure method from more than 10 layers.Relentless scaling brings big challenges to process integration and pushes each process module to the physical and material limit.Therefore,the success of process development will largely depend on careful balance the pros and cons to achieve both performance and yield targets.In the paper,we discussed the advantages and disadvantages of different process approaches for key process loops for 5 nm logic process flow,including dummy poly cut versus metal gate cut approaches in the metal gate loops,self-aligned contact(SAC)versus brutally aligned contact(BAC)approaches,and also introduced the self-aligned double patterning approach in the lower metal processes.Based on the above evaluation,we will provide a recommendation for module's process development.

Large Aperture Low Threshold Current 980nm VCSELs Fabricated with Pulsed Anodic Oxidation

Pulsed anodic oxidation technique, a new way of forming current blocking layers, was successfully used in ridge-waveguide QW laser fabrication. This method was applied in 980 nm VCSELs fabrication to form a high-quality native oxide current blocking layer, which simplifies the device process. A significant reduction of threshold current and a distinguished device performance are achieved. The 500 μm diameter device has a current threshold as low as 0.48 W. The maximum CW operation output power at room temperature is 1.48 W. The lateral divergence angle θ‖ and vertical divergence angle θ⊥ are as low as 15.3° and 13.8° without side-lobes at a current of 6 A.

Self-aligned graphene field-effect transistors on SiC(0001) substrates with self-oxidized gate dielectric

A scalable self-aligned approach is employed to fabricate monolayer graphene field-effect transistors on semi-insulated 4H-SiC （0001） substrates. The self-aligned process minimized access resistance and parasitic capacitance. Self-oxidized Al2O3, formed by deposition of 2 nm A1 followed by exposure in air to be oxidized, is used as gate dielectric and shows excellent insulation. An intrinsic cutoff frequency of 34 GHz and maximum oscillation frequency of 36.4 GHz are realized for the monolayer graphene field-effect transistor with a gate length of 0.2 μm. These studies show a pathway to fabricate graphene transistors for future applications in ultra-high frequency circuits.

High quality metal-quantum dot-metal structure fabricated with a highly compatible self-aligned process

A self-aligned process to fabricate a ＂metal-quantum dot-metal＂ structure is presented, based on an ＂electron beam lithography, thin film deposition and dry etching process＂. The sacrificial layers used can improve the lift-off process, and novel lithography layouts design can improve the mechanical strength of the fabricated nanostructures. The superiority of the self-aligned process includes low request for overlay accuracy, high compatibility with a variety of materials, and applicable to similar structure devices fabrication. Finally, a phase change memory with fully confined phase-change material node, with the length × width × height of 255 × 45 × 30 nm^3 was demonstrated.

SANTA： Self-aligned nanotrench ablation via Joule heating for probing sub-20 nm devices

Manipulating materials at the nanometer scale is challenging, particularly if alignment with nanoscale electrodes is desired. Here, we describe a lithography-free, self-aligned nanotrench ablation （SANTA） technique to create nanoscale ＂trenches＂ in a polymer like poly（methyl methacrylate） （PMMA）. The nanotrenches are self-aligned with carbon nanotube （CNT） or graphene ribbon electrodes through a simple Joule heating process. Using simulations and experiments we investigated how the Joule power, ambient temperature, PMMA thickness, and substrate properties affect the spatial resolution of this technique. We achieved sub-20 nm nanotrenches, for the first time, by lowering the ambient temperature and reducing the PMMA thickness. We also demonstrated a functioning nanoscale resistive memory （RRAM） bit self- aligned with a CNT control device, achieved through the SANTA approach. This technique provides an elegant and inexpensive method to probe nanoscale devices using self-aligned electrodes, without the use of conventional alignment or lithography steps.

LiNbO_3 Self-Aligned Ridge Waveguide with Dielectric Side Buffers

A simple fabrication method of self-aligned ridge waveguides with dielectric side buffers is demonstrated on +Z-cut LiNbO3. The ridge waveguide is fabricated by a combination of the annealed proton exchange process and the proton-exchanged wet etching technique.

A novel symmetrical split-gate structure for 2-bit per cell flash memory

A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection （SSI） and a poly-to-poly tunneling mechanism respectively.