Integrated Application of RS and GIS to Agriculture Land Use Planning

This paper gives some guidelines of land use planning firstly.A framework of agriculture land use planning is designed based on land use suitability evaluation using integrated technologies of RS and GIS.Further work expected is also given.

Application of Homemade DCS in Integrated BOP Control of 600-MW Supercritical Unit

The PLC and upper computer are used in BOP control system of traditional thermal power plant to monitor the in-situ equipment. It is complicated and wastes labor and resources. It is difficult to maintain and manage them. Beijing GuoDian ZhiShen Control Technology applied the homemade DCS (EDPF-NT System) to the integrated BOP control system of 600-MW supercritical power unit, which offers advantages in efficiency promotion, cost reduction and resource sharing. That also reflects the dominance of EDPF-NT System in performance, price, real-time DUP, network compatibility and communication. This article introduces the main characteristics, structure and configuration of EDPF-NT System, as well as the hierarchical operation, the multi-domain network structure and the private network router developed for Zhuanghe Power Plant.

China Association of Chinese Medicine Paper notice for seminar on clinical application of new technology of integrated Chinese and western medicine in treating sequelae of cerebrovascular diseases

Hosted by ChinaAssociation of Chinese Medicine,and organized by World Journal of Integrated traditional and western Medicine,seminar on clinical application of new technology of integrated Chinese and western medicine in treating sequelae of cerebrovascular diseases is planned to be held in Nanning,Guangxi in August.

Recent Requirements and Future Development of Integrated EMS/DTS System in China

Resent status for dispatch automation systems in China is introduced and the requirement for integrated EMS/DTS is discussed. The advantages of the integration of EMS/DTS are analyzed. Large benefit can be obtained to develop an integrated EMS/DTS system. EMS/DTS functions for district power system application are investigated and introduced. An application of the LINUX based EMS/DTS to Yulin power system is reported and is used to show the advantage of an open system. Future development of integrated EMS/DTS systems in China is discussed.

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

Computational Analysis of Performance for Heterogeneous Integrated System with Test Automation

Heterogeneity is inevitable in enterprises due to their various input requirements. The usage of proprietary integration products results in the increased cost of enterprises. During the integration, the focus area has been found to often address only the functional requirements, while the non-functional requirements are side-stepped during the initial stages of a project. Moreover, the use of proprietary integration products and non-standards-based integration platform has given rise to an inflexible integration infrastructure resulting in adaptability concerns. Web services-based integration, based on open standards, is deemed to be the only feasible solution in such cases. This paper explains the performance analysis of enterprise integration in heterogeneous environments for the distributed and the transactional applications. The analysis presented in this paper is seen as a step towards making intelligent decisions well in advance when choosing the integration mechanism/products to address the functional as well as the non-functional requirements considering the future integration needs.

Explore the application of educational information in College English Teaching

With the development of information technology, it has become a hot topic in higher education sector that integrate IT with other disciplines in university and bring it into the classroom. This paper demonstrates the integration of information technology and interactive college English teaching aiming to improve the efficiency of classroom teaching and the quality of teaching so as to achieve the modernization of education and cultivate modem talents in a better way.

THE CAUCHY TYPE INTEGRAL FOR M-ANALYTIC FUNCTION AND ITS APPLICATION

In this paper, the Cauchy type integral for M-analytic function is investigated which is by definition the regular solution of the elliptic system f_x+Mf_y=0, where M is a constant m×m matrix without any real eigenvalues and f is an m×q matrix.

Application of FPGA in Process Tomography Systems

This paper will provide some insights on the application of Field Programmable Gate Array (FPGA) in process tomography. The focus of this paper will be to investigate the performance of the technology with respect to various tomography systems and comparison to other similar technologies including the Application Specific Integrated Circuit (ASIC), Graphics Processing Unit (GPU) and the microcontroller. Fundamentally, the FPGA is primarily used in the Data Acquisition System (DAQ) due to its better performance and better trade-off as compared to competitor technologies. However, the drawback of using FPGA is that it is relatively more expensive.

The Strategy of Application Integration in Implementing PDM

Combining with real project three levels of application integration in implementing PDM are introduced in this paper. Based on the research on the integration ability between major PDM systems and CAD systems, this paper discusses the strategy of realizing the application integration in three levels.

ENTERPRISE INTEGRATION PLATFORM BASED ON SERVICEORIENTED ARCHITECTURE

To achieve information integration, process integration and application integration of enterprise, an enterprise integration platform （EIP） based on service-oriented architecture （SOA） is built. The enterprise integration model depending on encapsulating the business processes as well as the enterprise applications by the neutral and standard web services is presented. The problem how to discover the existed enterprise resources and share them was resolved depending on the mechanism of publishing and discovering the services. The EIP is integrated closely with product lifecycle management （PLM） system so that the process integration as well as orchestration of the business process services is implemented by encapsulating the workflow engine of PLM system. Not only process integration and application integration, but also information integration based on the bill of material （BOM） conversion driven by process are achieved. Finally, an interpretive, qualitative case study on EIP is conducted for this research.

Novel Frequency Hopping Sequences Generator Based on AES Algorithm

A novel frequency hopping(FH) sequences generator based on advanced encryption standard(AES) iterated block cipher is proposed for FH communication systems.The analysis shows that the FH sequences based on AES algorithm have good performance in uniformity, correlation, complexity and security.A high-speed, low-power and low-cost ASIC of FH sequences generator is implemented by optimizing the structure of S-Box and MixColumns of AES algorithm, proposing a hierarchical power management strategy, and applying ...

ASIC Design of Floating-Point FFT Processor

An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.

Research on metadata in manufacturing-oriented EAI

Enterprise application integration （EAI） focuses on the collaboration and interconnection of various information systems, so the basic problem to be solved is how EAI guarantees that the applications will produce consistent presentation of data, message and transaction. The metadata methodology may give us certain good ideas. First, the metadata description method of manufacturing information resource, transaction process and message delivery is put forward on the basis of operation analysis of manufacturing-oriented EAI, and then the tree-structured XML schema of corresponding object is built and a framework of metadata application in the discrete Manufacturing-Oriented EAI is established. Finally, a practical enterprise information integration system in Shanghai Tobacco Machine Co., Ltd. is presented as an example to show how it functions.

High-sensitivity integrated devices based on surface plasmon resonance for sensing applications

A metallic nanostructured array that scatters radiation toward a thin metallic layer generates surface plasmon resonances for normally incident light. The location of the minimum of the spectral reflectivity serves to detect changes in the index of refraction of the medium under analysis. The normal incidence operation eases its integration with optical fibers. The geometry of the arrangement and the material selection are changed to optimize some performance parameters as sensitivity, figure of merit, field enhancement, and spectral width. This optimization takes into account the feasibility of the fabrication. The evaluated results of sensitivity(1020 nm/RIU)and figure of merit(614 RIU^(-1)) are competitive with those previously reported.

Design of 3D Active Multichannel Silicon Neural Microelectrode

To find a design method for 3D active multichannel silicon microelectrode, a microstructure of active neural recording system is presented, where two 2D probes, two integrated circuits and two spacers are microassembled on a 5 mm×7 mm silicon platform, and 32 sites neural signals can be operated simultaneously. A theoretical model for measuring the neural signal by the silicon microelectrode is proposed based on the structure and fabrication process of a single-shank probe. The method of determining the dimensional parameters of the probe shank is discussed in the following three aspects, i.e. the structures of pallium and endocranium, coupled interconnecters noise, and strength characteristic of neural probe. The design criterion is to minimize the size of the neural probe as well as that the probe has enough stiffness to pierce the endocranium. The on-chip unity-gain bandpass amplifier has an overall gain of 42 dB over a bandwidth from 60 Hz to 10 kHz; and the DC-baseline stability circuit is of high input resistance above 30 MΩ to guarantee a cutoff frequency below 100 Hz. The circuit works in stimulating or recording modes. The conversion of the modes depends on the stimulating control signal.

Towards a Smallest Scale of Context in Ontology Integration

In order to solve the ambiguity problems in the semantic context （structure, granularity or scale） emerging in the process of ontology integration application, this paper analyzes the essential characters of context structure, proposes a novel semantic context generating algorithm, which is implemented over VO-Editor（visual ontology editor）, from the satisfiability-based point of view, and proves that the context entity generated by this algorithm is smallest in scale and unique. It offers a feasible means for developers to handle context problems for ontology integration application.

Reconfigurable Communication Processor: A New Approach for Network Processor

As the traditional RISC+ASIC/ASSP approach for network processor design can not meet the today’s requirements, this paper described an alternate approach, Reconfigurable Processing Architecture, to boost the performance to ASIC level while reserve the programmability of the traditional RISC based system. This paper covers both the hardware architecture and the software development environment architecture.

Modeling of the Bohai oilfield engineering geology demonstration information system based on digital seabed technology

In this paper, the framework and technologic process of engineering geology demonstration information system （EGDIS） of the Bohai oilfield are presented, and the key technologies for system modeling, such as storage and processing technology of multi-source and heterogeneous data, integrated display technology of multi-source information and multiple safeguard system design are studied. EGDIS of the Bohai oilfield is an integrated application system based on the data standardization and digital seabed database, has the function to realize the standardization/conformity, input/output, inquiry and display of the multi-source and heterogeneous data and graphics, and provides multiple comprehensive analysis and application services, which will provide shared and scientific basic data for the marine engineering construction and oilfield engineering safeguard.

0.18μm CMOS, MONOLITHIC MSTP ASIC

A highly integrated monolithic Multi-Service Transport Platform （MSTP） Application Specified Integrated Circuit （AS1C） MSEOSX8-6 has been fabricated with 0.18μm CMOS technology incorporating 26×10^6 transistors. The chip is designed to provide standard framing and mapping of 10/100/1000Mbit/s Ethernet, Resilient Packet Ring （RPR） and E1 traffics into protected Synchronous Digital Hierarchy （SDH） STM-1 transport payloads using hitless rate adaptation for optimum bandwidth utilization. It consumes 4W of power on average and utilizes 756 pin enhanced BGA package.