A soft,rough set model is a distinctive mathematical model that can be used to relate a variety of real-life data.In the present work,we introduce new concepts of rough set based on soft pre-lower and soft pre-upper a...A soft,rough set model is a distinctive mathematical model that can be used to relate a variety of real-life data.In the present work,we introduce new concepts of rough set based on soft pre-lower and soft pre-upper approximation space.These concepts are soft pre-rough equality,soft pre-rough inclusion,soft pre-rough belonging,soft predefinability,soft pre-internal lower,and soft pre-external lower.We study the properties of these concepts.Finally,we use the soft pre-rough approximation to illustrate the importance of our method in decision-making for Chikungunya medical illnesses.In reality,the impact factors of Chikungunya’s medical infection were determined.Moreover,we develop two new algorithms to address Chikungunya virus issues.Our proposed approach is sensible and effective.展开更多
A Taylor series expansion(TSE) based design for minimum mean-square error(MMSE) and QR decomposition(QRD) of multi-input and multi-output(MIMO) systems is proposed based on application specific instruction set process...A Taylor series expansion(TSE) based design for minimum mean-square error(MMSE) and QR decomposition(QRD) of multi-input and multi-output(MIMO) systems is proposed based on application specific instruction set processor(ASIP), which uses TSE algorithm instead of resource-consuming reciprocal and reciprocal square root(RSR) operations.The aim is to give a high performance implementation for MMSE and QRD in one programmable platform simultaneously.Furthermore, instruction set architecture(ISA) and the allocation of data paths in single instruction multiple data-very long instruction word(SIMD-VLIW) architecture are provided, offering more data parallelism and instruction parallelism for different dimension matrices and operation types.Meanwhile, multiple level numerical precision can be achieved with flexible table size and expansion order in TSE ISA.The ASIP has been implemented to a 28 nm CMOS process and frequency reaches 800 MHz.Experimental results show that the proposed design provides perfect numerical precision within the fixed bit-width of the ASIP, higher matrix processing rate better than the requirements of 5G system and more rate-area efficiency comparable with ASIC implementations.展开更多
基金supported by the Deanship of the Scientific Research at Najran University,Najran,Saudi Arabia[NU/-/SERC/10/603].
文摘A soft,rough set model is a distinctive mathematical model that can be used to relate a variety of real-life data.In the present work,we introduce new concepts of rough set based on soft pre-lower and soft pre-upper approximation space.These concepts are soft pre-rough equality,soft pre-rough inclusion,soft pre-rough belonging,soft predefinability,soft pre-internal lower,and soft pre-external lower.We study the properties of these concepts.Finally,we use the soft pre-rough approximation to illustrate the importance of our method in decision-making for Chikungunya medical illnesses.In reality,the impact factors of Chikungunya’s medical infection were determined.Moreover,we develop two new algorithms to address Chikungunya virus issues.Our proposed approach is sensible and effective.
基金Supported by the Industrial Internet Innovation and Development Project of Ministry of Industry and Information Technology (No.GHBJ2004)。
文摘A Taylor series expansion(TSE) based design for minimum mean-square error(MMSE) and QR decomposition(QRD) of multi-input and multi-output(MIMO) systems is proposed based on application specific instruction set processor(ASIP), which uses TSE algorithm instead of resource-consuming reciprocal and reciprocal square root(RSR) operations.The aim is to give a high performance implementation for MMSE and QRD in one programmable platform simultaneously.Furthermore, instruction set architecture(ISA) and the allocation of data paths in single instruction multiple data-very long instruction word(SIMD-VLIW) architecture are provided, offering more data parallelism and instruction parallelism for different dimension matrices and operation types.Meanwhile, multiple level numerical precision can be achieved with flexible table size and expansion order in TSE ISA.The ASIP has been implemented to a 28 nm CMOS process and frequency reaches 800 MHz.Experimental results show that the proposed design provides perfect numerical precision within the fixed bit-width of the ASIP, higher matrix processing rate better than the requirements of 5G system and more rate-area efficiency comparable with ASIC implementations.
