Before the late 2000s,China employed a diplomatic“next generation”approach to its territorial disputes in the South China Sea(SCS).Beginning in the late 2000s,however,China has assumed threatening attitudes,and take...Before the late 2000s,China employed a diplomatic“next generation”approach to its territorial disputes in the South China Sea(SCS).Beginning in the late 2000s,however,China has assumed threatening attitudes,and taken a strong stand against other disputants.Why has China recently shown its assertiveness when dealing with the South China Sea issue?This study argues that two factors-China’s growing naval capabilities and the growing presence of China’s strategic rivals around the South China Sea-led China to adopt a more assertive policy regarding the South China Sea issue.展开更多
John Dryden’s poem Mac Flecknoe satirizes his literary enemy Thomas Shadwell by the aid of the image of Flecknoewhile it reveals some of his literature assertions.This paper tries to expound them from the following t...John Dryden’s poem Mac Flecknoe satirizes his literary enemy Thomas Shadwell by the aid of the image of Flecknoewhile it reveals some of his literature assertions.This paper tries to expound them from the following three perspectives:the attitudes towards Ben Johnson,the proposals for drama language and the selection,and the attitudes towards French classicism forthe purpose of a further understanding about John Dryden.展开更多
Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion generation.While the simulation data is inherently incomplete,it is necessary to evaluate the truth...Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion generation.While the simulation data is inherently incomplete,it is necessary to evaluate the truth values of the mined assertions.This paper presents an approach to evaluating and constraining hardware assertions with absent scenarios.A Belief-fail Rate metric is proposed to predict the truth/falseness of generated assertions.By considering both the occurrences of free variable assignments and the conflicts of absent scenarios,we use the metric to sort true assertions in higher ranking and false assertions in lower ranking.Our Belief-failRate guided assertion constraining method leverages the quality of generated assertions.The experimental results show that the Belief-failRate framework performs better than the existing methods.In addition,the assertion evaluating and constraining procedure can find more assertions that cover new design functionality in comparison with the previous methods.展开更多
功能验证在处理器芯片开发流程中所占用的时间超过70%,因此优化提升功能验证环节的效率非常必要.软件仿真等传统验证方法提供了包括断言等多种验证机制,以提升验证的细粒度可见性和自检查能力,但是软件仿真运行速度较慢,在高效性方面有...功能验证在处理器芯片开发流程中所占用的时间超过70%,因此优化提升功能验证环节的效率非常必要.软件仿真等传统验证方法提供了包括断言等多种验证机制,以提升验证的细粒度可见性和自检查能力,但是软件仿真运行速度较慢,在高效性方面有明显不足.基于FPGA的硬件原型验证方法能极大地加速验证性能,但其调试能力较弱,虽能快速发现漏洞,但难以定位漏洞出现的具体位置和根本原因,存在有效性不足难题.为同时解决上述功能验证有效性与高效性的问题,提出一种将不可综合的断言语言SVA(SystemVerilog Assertion)自动转换成逻辑等效但可综合的RTL电路的方法,聚焦于断言这一类对设计进行非全局建模、纵向贯穿各抽象层级的验证方式,对基于全局指令集架构(instruction set architecture,ISA)模型的验证能力进行补足.同时,结合FPGA细粒度并行化、高度可扩展的优势,对处理器的验证过程进行硬件加速,提升了处理器的开发效率.实现了一个端到端的硬件断言平台,集成对SVA进行硬件化的完整工具链,并统计运行在FPGA上的硬件化断言的触发和覆盖率情况.实验表明,和软件仿真相比,所提方法能取得超过2万倍的验证效率提升.展开更多
G.Brewka presented a modified default logic (CDL) and obtained some properties of CDL,such as the existence of extensions,semimonotonicity,which the Reiters normal default logic shares.The Reiter’s default has been g...G.Brewka presented a modified default logic (CDL) and obtained some properties of CDL,such as the existence of extensions,semimonotonicity,which the Reiters normal default logic shares.The Reiter’s default has been generalized,a default logic about assertion’s has been obtained,and the assertion that the Brewka’s CDL is a special normal default logic of the new version has been proved.展开更多
文摘Before the late 2000s,China employed a diplomatic“next generation”approach to its territorial disputes in the South China Sea(SCS).Beginning in the late 2000s,however,China has assumed threatening attitudes,and taken a strong stand against other disputants.Why has China recently shown its assertiveness when dealing with the South China Sea issue?This study argues that two factors-China’s growing naval capabilities and the growing presence of China’s strategic rivals around the South China Sea-led China to adopt a more assertive policy regarding the South China Sea issue.
文摘John Dryden’s poem Mac Flecknoe satirizes his literary enemy Thomas Shadwell by the aid of the image of Flecknoewhile it reveals some of his literature assertions.This paper tries to expound them from the following three perspectives:the attitudes towards Ben Johnson,the proposals for drama language and the selection,and the attitudes towards French classicism forthe purpose of a further understanding about John Dryden.
基金supported in part by the National Natural Science Foundation of China under Grant Nos.61876173,61432017,and 61532017.
文摘Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion generation.While the simulation data is inherently incomplete,it is necessary to evaluate the truth values of the mined assertions.This paper presents an approach to evaluating and constraining hardware assertions with absent scenarios.A Belief-fail Rate metric is proposed to predict the truth/falseness of generated assertions.By considering both the occurrences of free variable assignments and the conflicts of absent scenarios,we use the metric to sort true assertions in higher ranking and false assertions in lower ranking.Our Belief-failRate guided assertion constraining method leverages the quality of generated assertions.The experimental results show that the Belief-failRate framework performs better than the existing methods.In addition,the assertion evaluating and constraining procedure can find more assertions that cover new design functionality in comparison with the previous methods.
文摘功能验证在处理器芯片开发流程中所占用的时间超过70%,因此优化提升功能验证环节的效率非常必要.软件仿真等传统验证方法提供了包括断言等多种验证机制,以提升验证的细粒度可见性和自检查能力,但是软件仿真运行速度较慢,在高效性方面有明显不足.基于FPGA的硬件原型验证方法能极大地加速验证性能,但其调试能力较弱,虽能快速发现漏洞,但难以定位漏洞出现的具体位置和根本原因,存在有效性不足难题.为同时解决上述功能验证有效性与高效性的问题,提出一种将不可综合的断言语言SVA(SystemVerilog Assertion)自动转换成逻辑等效但可综合的RTL电路的方法,聚焦于断言这一类对设计进行非全局建模、纵向贯穿各抽象层级的验证方式,对基于全局指令集架构(instruction set architecture,ISA)模型的验证能力进行补足.同时,结合FPGA细粒度并行化、高度可扩展的优势,对处理器的验证过程进行硬件加速,提升了处理器的开发效率.实现了一个端到端的硬件断言平台,集成对SVA进行硬件化的完整工具链,并统计运行在FPGA上的硬件化断言的触发和覆盖率情况.实验表明,和软件仿真相比,所提方法能取得超过2万倍的验证效率提升.
基金Project supported by the High Technology Research and Development Program of China.
文摘G.Brewka presented a modified default logic (CDL) and obtained some properties of CDL,such as the existence of extensions,semimonotonicity,which the Reiters normal default logic shares.The Reiter’s default has been generalized,a default logic about assertion’s has been obtained,and the assertion that the Brewka’s CDL is a special normal default logic of the new version has been proved.