The glacial extent and glacial advance/retreat asynchroncity in East Asia during Last Glaciation

New dates for last glacial cycle in Tibetan bordering mountains and in East Asia show the glacial extent during the early/middle （MIS3-4） stage is larger than that of the late stage （MIS2） in last glacial cycle. It is asynchronous with the Northern Hemisphere ice sheets maximum and changes in oceanic circulation that predominately control global climate. In research areas, three seasonal precipitation patterns control the accumulation and ablation of glaciers. The modes of the westerlies and the East Asian mountains/islands in and along the Pacific Ocean are favorable to glacier advance with mainly winter precipitation accumulation. There was a global temperature-decreasing phase in the middle stage （MIS3b, 54-44 ka BP）, when the glacier extent was larger than that in Last Glaciation Maximum due to the low temperature combined with high moisture. It is revealed that the Quaternary glaciers not only evolved with localization, but also maybe with globalization. The latest studies show a fact that the developmental characteristics of glaciers in high mountains or islands along the western Pacific Ocean are not in accord with those inland areas. Therefore, it can be concluded that glacier development exhibits regional differences. The study validates the reasonableness of the asynchronous advance theory, and ascertains that both the synchronous and asynchronous advance/retreat of glaciers existed from 30 ka BP to 10 ka BP. It is not suitable to emphasize the synchronicity between global ice-volume and glacier change.

An AES chip with DPA resistance using hardware-based random order execution

This paper presents an AES（advanced encryption standard） chip that combats differential power analysis （DPA） side-channel attack through hardware-based random order execution.Both decryption and encryption procedures of an AES are implemented on the chip.A fine-grained dataflow architecture is proposed,which dynamically exploits intrinsic byte-level independence in the algorithm.A novel circuit called an HMF（Hold-MatchFetch） unit is proposed for random control,which randomly sets execution orders for concurrent operations.The AES chip was manufactured in SMIC 0.18μm technology.The average energy for encrypting one group of plain texts（128 bits secrete keys） is 19 nJ.The core area is 0.43 mm^2.A sophisticated experimental setup was built to test the DPA resistance.Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack.Compared with the corresponding fixed order execution,the hardware based random order execution is improved by at least 21 times the DPA resistance.