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Privacy Preserving Solution for the Asynchronous Localization of Underwater Sensor Networks 被引量:9
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作者 Haiyan Zhao Jing Yan +1 位作者 Xiaoyuan Luo Xinping Guan 《IEEE/CAA Journal of Automatica Sinica》 SCIE EI CSCD 2020年第6期1511-1527,共17页
Location estimation of underwater sensor networks(USNs)has become a critical technology,due to its fundamental role in the sensing,communication and control of ocean volume.However,the asynchronous clock,security atta... Location estimation of underwater sensor networks(USNs)has become a critical technology,due to its fundamental role in the sensing,communication and control of ocean volume.However,the asynchronous clock,security attack and mobility characteristics of underwater environment make localization much more challenging as compared with terrestrial sensor networks.This paper is concerned with a privacy-preserving asynchronous localization issue for USNs.Particularly,a hybrid network architecture that includes surface buoys,anchor nodes,active sensor nodes and ordinary sensor nodes is constructed.Then,an asynchronous localization protocol is provided,through which two privacy-preserving localization algorithms are designed to estimate the locations of active and ordinary sensor nodes.It is worth mentioning that,the proposed localization algorithms reveal disguised positions to the network,while they do not adopt any homomorphic encryption technique.More importantly,they can eliminate the effect of asynchronous clock,i.e.,clock skew and offset.The performance analyses for the privacy-preserving asynchronous localization algorithms are also presented.Finally,simulation and experiment results reveal that the proposed localization approach can avoid the leakage of position information,while the location accuracy can be significantly enhanced as compared with the other works. 展开更多
关键词 asynchronous clock LOCALIZATION privacy preservation underwater sensor networks(USNs)
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Non-PLL high-precision synchronous sampling method among lots of acoustics acquisition channels for underwater multilinear array seismic exploration system
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作者 JIANG Jiajia CUI Jindong +6 位作者 WANG Xianquan LI Xiaodong ZENG Xianjun ZHOU Dasen YAO Qingwang DUAN Fajie FU Xiao 《Journal of Measurement Science and Instrumentation》 CAS CSCD 2022年第1期41-50,共10页
Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the proble... Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the problems of complex synchronous sampling method and long locking time after varying sampling rate in traditional underwater seismic exploration system,an improved synchronous sampling model based on the master-slave synchronous model and local clock asynchronous drive with non phase locked loop(PLL)is built,and a high-precision synchronous sampling method is proposed,which combines the short-term stability of local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock.Based on the improved synchronous sampling model,the influence of clock stability,transmission delay and phase jitter on synchronous sampling error is analyzed,and a high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed.The model and method effectively realize the immunity of phase jitter on synchronous sampling error in principle,and compensate the influence of signal transmission delay on synchronous sampling error.At the same time,it greatly reduces the complexity of software and hardware implementation of synchronous sampling,and solves the problem of long locking time after changing the sampling rate in traditional methods.The experimental system of synchronous sampling for dual linear array is built,and the synchronous sampling accuracy is better than 5 ns. 展开更多
关键词 seismic exploration system synchronous sampling non phase locked loop(PLL) local clock asynchronous drive transmission delay
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A single-channel 10-bit 160 MS/s SAR ADC in 65 nm CMOS
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作者 卢宇潇 孙麓 +1 位作者 李哲 周健军 《Journal of Semiconductors》 EI CAS CSCD 2014年第4期138-145,共8页
This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new wi... This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied. 展开更多
关键词 SAR ADC asynchronous clock SAR logic Bootstrapped switch
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