Location estimation of underwater sensor networks(USNs)has become a critical technology,due to its fundamental role in the sensing,communication and control of ocean volume.However,the asynchronous clock,security atta...Location estimation of underwater sensor networks(USNs)has become a critical technology,due to its fundamental role in the sensing,communication and control of ocean volume.However,the asynchronous clock,security attack and mobility characteristics of underwater environment make localization much more challenging as compared with terrestrial sensor networks.This paper is concerned with a privacy-preserving asynchronous localization issue for USNs.Particularly,a hybrid network architecture that includes surface buoys,anchor nodes,active sensor nodes and ordinary sensor nodes is constructed.Then,an asynchronous localization protocol is provided,through which two privacy-preserving localization algorithms are designed to estimate the locations of active and ordinary sensor nodes.It is worth mentioning that,the proposed localization algorithms reveal disguised positions to the network,while they do not adopt any homomorphic encryption technique.More importantly,they can eliminate the effect of asynchronous clock,i.e.,clock skew and offset.The performance analyses for the privacy-preserving asynchronous localization algorithms are also presented.Finally,simulation and experiment results reveal that the proposed localization approach can avoid the leakage of position information,while the location accuracy can be significantly enhanced as compared with the other works.展开更多
Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the proble...Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the problems of complex synchronous sampling method and long locking time after varying sampling rate in traditional underwater seismic exploration system,an improved synchronous sampling model based on the master-slave synchronous model and local clock asynchronous drive with non phase locked loop(PLL)is built,and a high-precision synchronous sampling method is proposed,which combines the short-term stability of local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock.Based on the improved synchronous sampling model,the influence of clock stability,transmission delay and phase jitter on synchronous sampling error is analyzed,and a high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed.The model and method effectively realize the immunity of phase jitter on synchronous sampling error in principle,and compensate the influence of signal transmission delay on synchronous sampling error.At the same time,it greatly reduces the complexity of software and hardware implementation of synchronous sampling,and solves the problem of long locking time after changing the sampling rate in traditional methods.The experimental system of synchronous sampling for dual linear array is built,and the synchronous sampling accuracy is better than 5 ns.展开更多
This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new wi...This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.展开更多
基金supported in part by the National Natural Science Foundation of China(61873345,61973263)the Youth Talent Support Program of Hebei(BJ2018050,BJ2020031)+2 种基金the Teturned Overseas Chinese Scholar Foundation of Hebei(C201829)the Natural Science Foundation of Hebei(F2020203002)the Postgraduate Innovation Fund Project of Hebei(CXZZSS2019047)。
文摘Location estimation of underwater sensor networks(USNs)has become a critical technology,due to its fundamental role in the sensing,communication and control of ocean volume.However,the asynchronous clock,security attack and mobility characteristics of underwater environment make localization much more challenging as compared with terrestrial sensor networks.This paper is concerned with a privacy-preserving asynchronous localization issue for USNs.Particularly,a hybrid network architecture that includes surface buoys,anchor nodes,active sensor nodes and ordinary sensor nodes is constructed.Then,an asynchronous localization protocol is provided,through which two privacy-preserving localization algorithms are designed to estimate the locations of active and ordinary sensor nodes.It is worth mentioning that,the proposed localization algorithms reveal disguised positions to the network,while they do not adopt any homomorphic encryption technique.More importantly,they can eliminate the effect of asynchronous clock,i.e.,clock skew and offset.The performance analyses for the privacy-preserving asynchronous localization algorithms are also presented.Finally,simulation and experiment results reveal that the proposed localization approach can avoid the leakage of position information,while the location accuracy can be significantly enhanced as compared with the other works.
基金National Key Research and Development Program of China(No.2018YFE0208200)National Natural Science Foundation of China(Nos.61971307,61905175,51775377)+5 种基金National Key Research and Development Plan Project(No.2020YFB2010800)The Fok Ying Tung Education Foundation(No.171055)China Postdoctoral Science Foundation(No.2020M680878)Guangdong Province Key Research and Development Plan Project(No.2020B0404030001)Tianjin Science and Technology Plan Project(No.20YDTPJC01660)Project of Foreign Affairs Committee of China Aviation Development Sichuan Gas Turbine Research Institute(Nos.GJCZ-2020-0040,GJCZ-2020-0041)。
文摘Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the problems of complex synchronous sampling method and long locking time after varying sampling rate in traditional underwater seismic exploration system,an improved synchronous sampling model based on the master-slave synchronous model and local clock asynchronous drive with non phase locked loop(PLL)is built,and a high-precision synchronous sampling method is proposed,which combines the short-term stability of local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock.Based on the improved synchronous sampling model,the influence of clock stability,transmission delay and phase jitter on synchronous sampling error is analyzed,and a high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed.The model and method effectively realize the immunity of phase jitter on synchronous sampling error in principle,and compensate the influence of signal transmission delay on synchronous sampling error.At the same time,it greatly reduces the complexity of software and hardware implementation of synchronous sampling,and solves the problem of long locking time after changing the sampling rate in traditional methods.The experimental system of synchronous sampling for dual linear array is built,and the synchronous sampling accuracy is better than 5 ns.
文摘This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.