A single channel,6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC

This paper presents a single channel, low power 6-bit 410-MS/s asynchronous successive approximation register analog-to-digital converter （SAR ADC） for ultrawide bandwidth （UWB） communication, prototyped in a SMIC 65-nm process. Based on the 3 bits/stage structure, resistive DAC, and the modified asynchronous successive approximation register control logic, the proposed ADC attains a peak spurious-free dynamic range （SFDR） of 41.95 dB, and a signal-to-noise and distortion ratio （SNDR） of 28.52 dB for 370 MS/s. At the sampling rate of 410 MS/s, this design still performs well with a 40.71-dB SFDR and 30.02-dB SNDR. A four-input dynamic comparator is designed so as to decrease the power consumption. The measurement results indicate that this SAR ADC consumes 2.03 mW, corresponding to a figure of merit of 189.17 fJ/step at 410 MS/s.

An 8 bit 12 MS/s asynchronous successive approximation register ADC with an on-chip reference

This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers. A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is calculated theoretically to ensure linearity. Asynchronous control logic is proposed to eliminate the high internal clocks and significantly speeds up the successive approximation algorithm. An on-chip reference with a fully integrated buffer and decoupling capacitor is adopted for avoiding an extra pin for the off-chip reference. The prototype, fabricated in UMC 0.18 um CMOS technology, achieves an effective number of bits of 7.64 bits at a sampling frequency of 12 MS/s. The total power consumption is 0.918 mW for a 1.8 V supply, while the onchip reference consumes 53% of the total power. It achieves a figure of merit of 180 fJ/conv-step, excluding the reference＇s power consumption.

Design and simulation of a 12-bit,40 MSPS asynchronous SAR ADC for the readout of PMT signals

High precision and large dynamic range measurement ave required in the readout systems for the Water Cherenkov Detector Array （WCDA） in the Large High Altitude Air Shower Observatory （LHAASO）. This paper presents a prototype of a 12-bit 40 MSPS Analog-to-Digital Converter （ADC） Application Specific Integrated Circuit （ASIC） designed for the readout of the LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on a power-efficient Successive Approximation Register （SAR） architecture, which incorporates key parts such as a Capacitive Digital-to-Analog Converter （CDAC）, dynamic compavator and asyn- chronous SAR control logic. The simulation results indicate that the Effective Number Of Bits （ENOB） with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are good enough for the readout requirements of the WCDA.

A single channel, 6-bit 230-MS/s asynchronous SAR ADC based on 2 bits/stage

This paper proposes a single channel, 6-bit 230-MS/s asynchronous successive approximation register analog-to-digital converter （ADC） in an SMIC 65 nm CMOS technology. Through adopting the modified 2 bits/stage asynchronous control logic, the presented ADC actualizes a peak 40.90-dB spurious-free dynamic range and 29.05-dB signal-to-noise and distortion ratio at 230-MS/s sampling rate. Utilizing the dynamic comparator without the preamplifier, this work attains low-power design with only 0.93 mW power consumption and accomplishes a figure of merit of 174.67 fJ/step at 1 V supply voltage.