An asynchronous wrapper with novel handshake circuits for data communication in globally asynchronous locally synchronous （GALS） systems is proposed. The handshake circuits include two communication ports and a loca...An asynchronous wrapper with novel handshake circuits for data communication in globally asynchronous locally synchronous （GALS） systems is proposed. The handshake circuits include two communication ports and a local clock generator. Two approaches for the implementation of communication ports are presented, one with pure standard cells and the others with Mttller-C elements. The detailed design methodology for GALS systems is given and the circuits are validated with VHDL and circuits simulation in standard CMOS technology.展开更多
For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips,this paper proposes a quasi delay-insensitive high-speed two-phase operation...For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips,this paper proposes a quasi delay-insensitive high-speed two-phase operation mode asynchronous wrapper.The metastable state in sampling data procedure can be avoided by detecting the write/read signal, which can be used to stop the clock.Empty/full level of the registers can be determined by detecting the pulse signal of the two-phase asynchronous register,and then control the wrapper to sample input/output data.Sender wrapper and receiver wrapper consist of C elements and threshold gates,which ensure the quasi delay-insensitive characteristics and enhance the robustness.Simulations under different technology corners are implemented based on SMIC 0.18μm standard CMOS. Sender wrapper and receiver wrapper allow synchronous modules to work at the speed of 3.08 GHz and 2.98 GHz respectively with average dynamic power consumption of 1.727 mW and 1.779 mW.Its advantages of high-throughput,low-power, scalability and robustness make it a viable option for high-speed low-power interconnection of network-on-chip.展开更多
文摘An asynchronous wrapper with novel handshake circuits for data communication in globally asynchronous locally synchronous （GALS） systems is proposed. The handshake circuits include two communication ports and a local clock generator. Two approaches for the implementation of communication ports are presented, one with pure standard cells and the others with Mttller-C elements. The detailed design methodology for GALS systems is given and the circuits are validated with VHDL and circuits simulation in standard CMOS technology.
基金Supported by the National Natural Science Foundation of China under Grant Nos.60725415,60971066the National High-Tech Research and Development 863 Program of China under Grant Nos.2009AA01Z258,2009AA01Z260the National Science & Technology Important Project under Grant No.2009ZX01034-002-001-005.
文摘For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips,this paper proposes a quasi delay-insensitive high-speed two-phase operation mode asynchronous wrapper.The metastable state in sampling data procedure can be avoided by detecting the write/read signal, which can be used to stop the clock.Empty/full level of the registers can be determined by detecting the pulse signal of the two-phase asynchronous register,and then control the wrapper to sample input/output data.Sender wrapper and receiver wrapper consist of C elements and threshold gates,which ensure the quasi delay-insensitive characteristics and enhance the robustness.Simulations under different technology corners are implemented based on SMIC 0.18μm standard CMOS. Sender wrapper and receiver wrapper allow synchronous modules to work at the speed of 3.08 GHz and 2.98 GHz respectively with average dynamic power consumption of 1.727 mW and 1.779 mW.Its advantages of high-throughput,low-power, scalability and robustness make it a viable option for high-speed low-power interconnection of network-on-chip.
