2.7-4.0 GHz PLL with dual-mode auto frequency calibration for navigation system on chip

A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.

A 5-GHz frequency synthesizer with constant bandwidth for low IF ZigBee transceiver applications

A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.