Cancellation for frequency offset in OFDM system based on TF-LMS algorithm

In an orthogonal frequency division multiplexing(OFDM) system,a time and frequency domain least mean square algorithm(TF-LMS) was proposed to cancel the frequency offset(FO).TF-LMS algorithm is composed of two stages.Firstly,time domain least mean square(TD-LMS) scheme was selected to pre-cancel the frequency offset in the time domain,and then the interference induced by residual frequency offset was eliminated by the frequency domain mean square(FD-LMS) scheme in frequency domain.The results of bit error rate(BER) and quadrature phase shift keying(QPSK) constellation figures show that the performance of the proposed suppression algorithm is excellent.

An iterative interference cancellation based frequency offset estimation method for OFDMA uplink systems

In this paper, Moose scheme is used for frequency offset estimation in OFDMA uplink svstems due to that the signals from different users can be easily distinguished in frequency domain. However, differential multiple access interference （MAI） will deteriorate the frequency offset estimation performances, especially in interleaved OFDMA system. Analysis and simulation results manifest that frequency offset estimation by Moose scheme in block OFDMA system is more robust than that in interleaved OFDMA systern. And an iterative interference cancellation method has been proposed to suppress the differential MAI interference for interleaved OFDMA system, in which Moose scheme is the special case of the number of iteration is equal to one. Simulation results demonstrate that the proposed method can improve the performance with the increase of the number of iterations. In consideration of the performance and complexity, the proposed method with two iterations is selected. And the full comparison results of the proposed iterative method with two iterations and that with one iteration （conventional Moose scheme） are given in the paper, which sufficiently demonstrate that the performance gain can be obtained by the interference cancellation operation in interleaved OFDMA system.

CMOS Automatic Gain Control Circuit with DC Offset Cancellation for FM/cw Ladar

This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.

Optimum weighting-coefficient-pair in inter-carrier interference self-cancellation scheme of OFDM system

As one of the most important components of the wideband wireless access technique, orthogonal frequency division multiplexing （OFDM） has a high usage rate of spectrum and combats inter-symbol interference （ISI） in multi-path fading channel. However, when there are frequency offsets during the signal transmission, the inter-carrier interference （ICI） is introduced, which significantly degrades the performance. The existing ICI self-cancellation schemes such as PCC-OFDM are not optimum to minimize the interference considering both noise and ICI. In this paper, a new metric named S1NR （signal-to-interference- and-noise ratio） is proposed. We discuss the optimization issue when a constant frequency offset exists and in time-varying channels. The optimum weighting-coefficient-pair （OWCP） is obtained, which maximizes SINR theoretically through the alternant iteration algorithm. Simulations show that the performance of OWCP-OFDM is better than that of PCC-OFDM, especially when the frequency offset is large. Although the ICI self-cancellation scheme suffers bandwidth inefficiency, from the simulation results we can also see that the performance of OWCP-OFDM is much better than that of the standard OFDM systems with the same bandwidth efficiency when a frequency offset exists. Moreover, since the redundant modulation provides the capability to suppress ICI as well as a receiving SNR gain, it can be considered as exchanging the bandwidth for SNR.

A single-ended 10-bit 200 kS/s 607 μ W SAR ADC with an auto-zeroing offset cancellation technique

Thispaperpresentsasingle-ended8-channel 10-bit200kS/s 607 #W synchronous successiveapproxi- mation register （SAR） analog-to-digital converter （ADC） using HLMC 55 nm low leakage （LL） CMOS technology with a 3.3 V/1.2 V supply voltage. In conventional binary-encoded SAR ADCs the total capacitance grows expo- nentially with resolution. In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area. The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array. The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures. This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV. The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 167 × 87 μm2. It shows a sampling rate of 200 kS/s and low power dissipation of 607/μW operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage. At the input frequency of 10 kHz the signal-to-noise-and- distortion ratio （SNDR） is 60.1 dB and the spurious-free dynamic range （SFDR） is 68.1 dB. The measured DNL is ±0.37/-0.06 LSB and INL is ±0.58/-0.22 LSB.

一种100 MHz~4 GHz宽带抗干扰射频接收机的设计

为满足导航、通信、相控阵雷达以及电子对抗等领域对高性能接收终端的需求,提高系统的抗干扰、通用化和小型化性能,设计了一款工作频率在100 MHz~4 GHz的宽带抗干扰接收机芯片。接收机结构采用直接下变频形式,包括单转差巴伦、无源混频器和移相器等,能够有效抑制频带内的干扰信号,在强干扰信号下整个接收机通道不阻塞,能检测出极小的有用信号,同时保证与没有干扰状态相比性能不恶化。针对零中频(zero-Intermediate Frequency,zero-IF)接收机容易产生本振泄露、自混频等现象,设计了直流失调校准、本振相位调整等功能,可实现直流偏置点5 mV的补偿。射频输入100 MHz~4 GHz变化时,混频器转换增益≥31.2 dB。

一款用于双向传输高速接口的阻抗校准电路

在具有双向传输功能的高速串行接口中,发射机输出端的两个电阻对电路性能有很大的影响。为提升电路在复杂环境中的工作性能,需要对电阻进行阻抗校准。传统的阻抗校准存在着功耗高、面积大、系统误差大、收敛时间长等缺点。针对上述问题,设计了一款用于双向传输高速串行接口的阻抗校准电路,通过共用电流源的方式有效地减小了阻抗校准电路的面积及功耗,并消除了电流源失配带来的系统误差;引入了带有失调消除的比较器,并对比较器中存在的开关管漏电及时钟馈通等效应进行优化,降低了校准电路的系统误差;使用了逐次逼近寄存器(Successive Approximation Register,SAR)逻辑对最佳的电阻校准控制码进行查找,从而减小了收敛时间。在SMIC 40 nm工艺上实现了一款高精度,低功耗,且可对两个电阻分别进行调节的阻抗校准电路。对两个待校准电阻进行蒙特卡洛分析,阻抗校准的3σ值分别为201.76 mΩ,198.80 mΩ,阻抗校准电路整体功耗为4.205 mW。

Interference-Cancellation-Based Carrier Frequency Offset Estimation for OFDMA Uplink Transmissions

A carrier frequency offset （CFO） estimator was developed based on an interference cancellation scheme for an orthogonal frequency division multiplex access uplink. An initial CFO estimate was first ob- tained based on the received training signals at each user＇s prescribed subcarder positions. Then, the re- ceived training signals were compensated by using the initial CFO estimates in the frequency domain and the multi-user interferences were estimated. Finally, the interference-cancelled training signals were used to reliably estimate each user＇s CFO. The CFO estimator performance was evaluated by the bit error rate per- formances of the CFO compensation-based receivers at the base station. Simulations show that with this optima CFO compensation receiver, the performance gain with the esti- mated CFO values is approximately 3 dB better at the 0.1% bit error rate than the initial CFO estimates.

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier（PGA） can be converted to an analog controlled dB-linear VGA. An operational amplifier（OPAMP） utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation（DCOC） loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm^2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency（HPCF） and the measured residual DC offset at the output of VGA is less than 2 mV.

A 10-Gb/s inductor-less variable gain amplifier with a linear-in-dB characteristic and DC-offset cancellation

This paper presents a broadband inductor-less variable gain amplifier （VGA） with a linear-in-dB gain control characteristic and DC-offset cancellation. The proposed VGA is composed of a variable gain block, an exponential voltage generator, a DC-offset canceller with common-mode voltage correction, and a gain peaking block. To achieve the broad band and reduce the chip area, the gain peaking block employs an inductor-less gain peaking scheme to compensate the high frequency gain drop of the variable gain block and the DC-offset canceller. The VGA fabricated in 0.13μm SiGe BiCMOS technology achieves a 3-dB bandwidth of 7.5 GHz and a variable gain range from -10 to 30 dB. Due to the inductor-less design, the die area is only 0.53 - 0.27 mm＆2 which is the smallest among other similar reported works. At 10-Gb/s, the VGA consumes 50 mW power from a single 1.2 V supply and exhibits an output data jitter of less than 30 pSpp.

一种用于ADC电路的高速高精度比较器设计

在分析各种比较器设计失调消除技术基础上,提出了一种用于ADC电路的高速高精度比较器设计技术和失调消除技术.该比较器由主动复位和被动箝位的预放大器和输出锁存器构成,具有失调自动校准功能.仿真结果表明,在Chartered 0.35μm COMS工艺下,电源电压3.3 V,调整后的比较器失调误差为56.8μV,比较器的精度0.1mV,比较速率100 MHz.

一种消除失调的开关电容带隙基准电路

本文介绍了一种基于开关电容的带隙基准芯片电路.本文巧妙地利用电容和开关的模拟电阻,实现了静态电流小,温度系数好的开关型基准电压.同时运用自动调零技术,克服了线性基准的失调缺陷,消除了运放的失调电压,提高了输出电压的失调精度.电路在0.5μm VIS CMOS工艺下实现,温度系数29×10-6V/℃,20mV输入失调电压下的电压漂移仅为0.4mV.

逐次逼近A/D转换器综述

从逐次逼近A/D转换器(SA-A/D)的工作原理出发,分别对其核心模块D/A转换器和比较器进行了讨论。SA-A/D转换器中的D/A转换器可分为电压定标、电流定标和电荷定标三种,重点分析了三种目前应用较多的并行电容、分段电容和RC混合结构。SA-A/D转换器中的比较器可分为运放结构比较器和锁存(latch)比较器,实际常常使用这两种结构级联的高速高精度比较器,并配合失调校准技术,达到较高精度。最后,简要总结了SA-A/D转换器的研究现状,阐述了其在精度、速度和功耗三个方面的发展状况。

一种低失调CMOS比较器设计

本文在研究各种比较器失调消除技术基础上,提出了一种用于ADC电路的高速高精度比较器失调消除技术。该比较器由主动复位和共模箝位的预放大器和输出锁存器构成,通过负反馈自适应调整比较器输入失调电压,降低了开关电容沟道电荷注入和时钟馈通对比较器精度的影响。仿真结果表明,在Chartered 0.35μm COMS工艺下,电源电压3.3V,调整后的比较器失调误差为34μV,比较速率100MHz。

一种高精密集成运算放大器的研制

基于运算放大器的基本原理和一些关键技术(基流自举补偿、偏置微调等)的运用,成功地研制出一种双极型高精度低失调集成运算放大器。测试结果显示,该运算放大器失调电压仅为10μV,失调电流小于1 nA,开环增益为120 dB,单位增益带宽680 kHz。

一种0.2-mV 20-MHz 600-μW比较器

提出了一种低功耗中速高精度比较器。比较器采用3级前置放大器加锁存器的多级结构,应用失调校准技术,用于一个电压2.5 V、速度1 MS/s、精度12位的逐次逼近型A/D转换器。该比较器采用UMC 0.18μm混合模式3.3 V CMOS工艺设计制造。仿真结果表明,在2.5 V电压下,速度可以达到20 MHz,准确比较0.2 mV电压,并能有效校准20 mV输入失调,功耗仅为600μW,版图面积为620μm×190μm。

两个重要改进提高了RFID读写器的性能

基于无源电子标签的RFID读写器系统通常采用所谓"零中频"接收方案,采用该方案会造成射频信号发射端和接收端之间的载波泄漏,其结果是一方面接收机前端容易饱和因而减少了系统通信距离;另一方面会带来所谓的"直流偏移"问题从而增加了系统误码率.本文提出了两个措施来解决或改善这一问题.首先,将载波抵消技术应用到2.45GHz频段的RFID读写器中,采用微带电路进行载波泄漏抵消电路的设计,通过ADS软件仿真、制作并测试样机,文中给出了改进后环行器泄漏功率的抵消结果.其次,提出一种带有直流反馈环路的宽带高增益直流放大器,用于放大基带信号并自动补偿混频器带来的直流分量,输出波形无明显失真,从而降低了读写器读取电子标签数据的误码率.

基于并行干扰抵消的OFDM/OQAM系统中的信号检测方法

在多径衰落信道中,基于交错正交幅度调制的正交频分复用(OFDM with Offset QAM,OFDM/OQAM)系统使用迫零均衡器进行信号检测时,不能完全消除信道复数特性和滤波器实数正交特性引入的时域符号间干扰和频域子载波间干扰,及信道估计误差导致的误码率性能损失。该文利用对数据初始判决并重构相邻载波及符号间干扰的思想,通过分析采用迫零均衡信号检测时的残余干扰与信道估计误差干扰,提出了一种基于并行干扰抵消和迫零均衡器结合的OFDM/OQAM信号检测方法,并在IEEE 802.22技术标准的两种典型多径衰落信道中进行了计算机仿真与比较研究。仿真结果表明,与基于迫零均衡的检测方法相比,基于并行干扰抵消的迭代信号检测方法在误码率为1%时,可获得1 dB至2 dB的性能提升。