This study proposes a new topology optimization solution providing designers with choices for feasible stiffener layouts inside large-scale containers of garbage trucks. Firstly, the mathematical expressions of loadin...This study proposes a new topology optimization solution providing designers with choices for feasible stiffener layouts inside large-scale containers of garbage trucks. Firstly, the mathematical expressions of loading conditions inside garbage containers are derived. Then, a growth-based layout optimization framework is built, taking inspiration from the morphology of plant ramifications. The principles of the highly effective but individual design rules of existent leaf venation layout problems are explored and transferred into analytical laws. Based on this, an evolutionary algorithm is developed to simulate the load-adapted growth of stiffener layouts, which provides an approximately homogeneous stress distribution along the surface of self-optimizing structures, Unlike the conventional methods, the new approach needs neither the densest ground structure nor the modification of the existing finite element programs, it is fast, easy to apply and nearly constraint free. Finally, a case study is provided showing how a large-scale container structure can be designed by this extremely intelligent CAD approach.展开更多
In the sub-wavelength regime,design for manufacturability（DFM） becomes increasingly important for field programmable gate arrays（FPGAs）.In this paper,an automated tile generation flow targeting micro-regular fabri...In the sub-wavelength regime,design for manufacturability（DFM） becomes increasingly important for field programmable gate arrays（FPGAs）.In this paper,an automated tile generation flow targeting micro-regular fabric is reported.Using a publicly accessible,well-documented academic FPGA as a case study,we found that compared to the tile generators previously reported,our generated micro-regular tile incurs less than 10%area overhead,which could be potentially recovered by process window optimization,thanks to its superior printability. In addition,we demonstrate that on 45 nm technology,the generated FPGA tile reduces lithography induced process variation by 33%,and reduce probability of failure by 21.2%.If a further overhead of 10%area can be recovered by enhanced resolution,we can achieve the variation reduction of 93.8%and reduce the probability of failure by 16.2%.展开更多
基金Acknowledgment The work reported in this paper is supported by the National Natural Science Foundation of China （Grant No. 51405377）, and the Hi-Tech Research and Development Program of China （Grant No. 2012AA040701）.
文摘This study proposes a new topology optimization solution providing designers with choices for feasible stiffener layouts inside large-scale containers of garbage trucks. Firstly, the mathematical expressions of loading conditions inside garbage containers are derived. Then, a growth-based layout optimization framework is built, taking inspiration from the morphology of plant ramifications. The principles of the highly effective but individual design rules of existent leaf venation layout problems are explored and transferred into analytical laws. Based on this, an evolutionary algorithm is developed to simulate the load-adapted growth of stiffener layouts, which provides an approximately homogeneous stress distribution along the surface of self-optimizing structures, Unlike the conventional methods, the new approach needs neither the densest ground structure nor the modification of the existing finite element programs, it is fast, easy to apply and nearly constraint free. Finally, a case study is provided showing how a large-scale container structure can be designed by this extremely intelligent CAD approach.
文摘In the sub-wavelength regime,design for manufacturability（DFM） becomes increasingly important for field programmable gate arrays（FPGAs）.In this paper,an automated tile generation flow targeting micro-regular fabric is reported.Using a publicly accessible,well-documented academic FPGA as a case study,we found that compared to the tile generators previously reported,our generated micro-regular tile incurs less than 10%area overhead,which could be potentially recovered by process window optimization,thanks to its superior printability. In addition,we demonstrate that on 45 nm technology,the generated FPGA tile reduces lithography induced process variation by 33%,and reduce probability of failure by 21.2%.If a further overhead of 10%area can be recovered by enhanced resolution,we can achieve the variation reduction of 93.8%and reduce the probability of failure by 16.2%.
