Off-state avalanche breakdown induced degradation in 20 V NLDMOS devices

Degradation behaviors of 20 V NLDMOS operated under off-state avalanche breakdown conditions are presented.A constant current pulse stressing test is applied to the device.Two different degradation mechanisms are identified by analysis of electrical data,technology computer-aided design（TCAD） simulations and charge pumping measurements.The first mechanism is attributed to positive oxide-trapped charges in the N-type drift region,and the second one is due to decreased electron mobility upon interface state formation in the drift region.Both of the mechanisms are enhanced with increasing avalanche breakdown current.

Backside optimization for improving avalanche breakdown behavior of 4.5 kV IGBT

The static avalanche breakdown behavior of 4.5 kV high-voltage IGBT is studied by theory analysis and experiment. The avalanche breakdown behaviors of the 4.5 kV IGBTs with different backside structures are investigated and compared by using the curve tracer. The results show that the snap back behavior of the breakdown waveform is related to the bipolar PNP gain, which leads to the deterioration of the breakdown voltage. There are two ways to optimize the backside structure, one is increasing the implant dose of the N^＋ buffer layer, the other is decreasing the implant dose of the P^＋ collector layer. It is found that the optimized structure is effective in suppressing the snap back behavior and improving the breakdown characteristic of high voltage IGBT.

The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure

A high-side thin-layer silicon-on-insulator （SOI） pLDMOS is proposed, adopting field implant （FI） and multiple field plate （MFP） technologies. The breakdown mechanisms of back gate （BG） turn-on, surface channel punch-through, and vertical and lateral avalanche breakdown are investigated by setting up analytical models, simulating related parameters and verifying experimentally. The device structure is optimized based on the above research. The shallow junction achieved through FI technology attenuates the BG effect, the optimized channel length eliminates the surface channel punch-through, the advised thickness of the buried oxide dispels the vertical avalanche breakdown, and the MFP technology avoids premature lateral avalanche breakdown by modulating the electric field distribution. Finally, for the first time, a 300 V high-side pLDMOS is experimentally realized on a 1.5 μm thick thin-layer SOI.

Low-voltage and high-gain WSe_(2)avalanche phototransistor with an out-of-plane WSe_(2)/WS_(2)heterojunction

The properties of photodetectors based on two-dimensional materials can be significantly enhanced by avalanche effect.However,a high avalanche breakdown voltage is needed to reach impact ionization,which leads to high power consumption.Here,we report the unique features of a low-voltage avalanche phototransistor formed by an in-plane WSe_(2)field effect transistor(FET)with an out-of-plane WSe_(2)/WS_(2)P–N heterojunction(HJ FET).The avalanche breakdown voltage in the device can be decreased from−31 to−8.5 V when compared with that in WSe_(2)FET.The inherent mechanism is mainly related to the redistributed electric field in the WSe_(2)channel after the formation of the out-of-plane P–N heterojunction.When the bias voltage is−16.5 V,the photoresponsivity in the HJ FET is enhanced from 1.5 to 135 A/W,which is significantly higher than that in the WSe_(2)FET because of the obvious reduction of the avalanche breakdown voltage.Moreover,HJ FET shows a higher responsivity than WSe_(2)FET in the range of 400–1,100 nm under low bias voltage.This phenomenon is caused by accelerating electron–hole spatial separation in the heterojunction.These results indicate that the use of an WSe_(2)FET with an out-of-plane WSe_(2)/WS_(2)heterojunction is ideal for high-performance photodetectors with low power consumption.

Investigation and modeling of the avalanche effect in MOSFETs with non-uniform finger spacing

This paper investigates the effect of a non-uniform gate-finger spacing layout structure on the avalanche breakdown performance of RF CMOS technology. Compared with a standard multi-finger device with uniform gate-finger spacing, a device with non-uniform gate-finger spacing represents an improvement of 8.5% for the drain-source breakdown voltage （BVds） and of 20% for the thermally-related drain conductance. A novel compact model is proposed to accurately predict the variation of BVds with the total area of devices, which is dependent on the different finger spacing sizes. The model is verified and validated by the excellent match between the measured and simulated avalanche breakdown characteristics for a set of uniform and non-uniform gate-finger spacing arranged nMOSFETs.

Design and optimization analysis of dual material gate on DG-IMOS

An impact ionization MOSFET （IMOS） is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope （SS） of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET （DG-IMOS） is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG （dual material gate） DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better IoN, ION/IoFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized perform- ance is achieved including ION/IoFF ratio of 2.87 × 10^9 A/μm with/ON as 11.87 × 10^-4 A/μm and transconductance of 1.06× 10^-3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.