In recent years,multiple-load automatic guided vehicle(AGV)is increasingly used in the logistics transportation fields,owing to the advantages of smaller fleet size and fewer occurrences of traffic congestion.However,...In recent years,multiple-load automatic guided vehicle(AGV)is increasingly used in the logistics transportation fields,owing to the advantages of smaller fleet size and fewer occurrences of traffic congestion.However,one main challenge lies in the deadlock-avoidance for the dispatching process of a multiple-load AGV system.To prevent the system from falling into a deadlock,a strategy of keeping the number of jobs in the system(NJIS)at a low level is adopted in most existing literatures.It is noteworthy that a low-level NJIS will make the processing machine easier to be starved,thereby reducing the system efficiency unavoidably.The motivation of the paper is to develop a deadlock-avoidance dispatching method for a multiple-load AGV system operating at a high NJIS level.Firstly,the deadlock-avoidance dispatching method is devised by incorporating a deadlock-avoidance strategy into a dispatching procedure that contains four sub-problems.In this strategy,critical tasks are recognized according to the status of workstation buffers,and then temporarily forbidden to avoid potential deadlocks.Secondly,three multiattribute dispatching rules are designed for system efficiency,where both the traveling distance and the buffer status are taken into account.Finally,a simulation system is developed to evaluate the performance of the proposed deadlock-avoidance strategy and dispatching rules at different NJIS levels.The experimental results demonstrate that our deadlock-avoidance dispatching method can improve the system efficiency at a high NJIS level and the adaptability to various system settings,while still avoiding potential deadlocks.展开更多
芯粒集成逐渐成为不同场景下敏捷定制深度学习芯片的高可扩展性的解决方案,芯片设计者可以通过集成设计、验证完成的第三方芯粒来降低芯片开发周期和成本,提高芯片设计的灵活性和芯片良率.在传统的芯片设计和商业模式中,编译器等专用软...芯粒集成逐渐成为不同场景下敏捷定制深度学习芯片的高可扩展性的解决方案,芯片设计者可以通过集成设计、验证完成的第三方芯粒来降低芯片开发周期和成本,提高芯片设计的灵活性和芯片良率.在传统的芯片设计和商业模式中,编译器等专用软件工具链是芯片解决方案的组成部分,并在芯片性能和开发中发挥重要作用.然而,当使用第三方芯粒进行芯片敏捷定制时,第三方芯粒所提供的专用工具链无法预知整个芯片的资源,因此无法解决敏捷定制的深度学习芯片的任务部署问题,而为敏捷定制的芯片设计全新的工具链需要大量的时间成本,失去了芯片敏捷定制的优势.因此,提出一种面向深度学习集成芯片的可扩展框架(scalable framework for integrated deep learning chips)--Puzzle,它包含从处理任务输入到运行时管理芯片资源的完整流程,并自适应地生成高效的任务调度和资源分配方案,降低冗余访存和芯粒间通信开销.实验结果表明,该可扩展框架为深度学习集成芯片生成的任务部署方案可自适应于不同的工作负载和硬件资源配置,与现有方法相比平均降低27.5%的工作负载运行延迟.展开更多
基金supported by the National Natural Science Foundation of China(Nos.52005427,61973154)the National Defense Basic Scientific Research Program of China(No.JCKY2018605C004)+1 种基金the Natural Science Research Project of Jiangsu Higher Education Institutions(Nos.19KJB510013,18KJA460009)the Foundation of Graduate Innovation Center in Nanjing University of Aeronautics and Astronautics(No.KFJJ20190516)。
文摘In recent years,multiple-load automatic guided vehicle(AGV)is increasingly used in the logistics transportation fields,owing to the advantages of smaller fleet size and fewer occurrences of traffic congestion.However,one main challenge lies in the deadlock-avoidance for the dispatching process of a multiple-load AGV system.To prevent the system from falling into a deadlock,a strategy of keeping the number of jobs in the system(NJIS)at a low level is adopted in most existing literatures.It is noteworthy that a low-level NJIS will make the processing machine easier to be starved,thereby reducing the system efficiency unavoidably.The motivation of the paper is to develop a deadlock-avoidance dispatching method for a multiple-load AGV system operating at a high NJIS level.Firstly,the deadlock-avoidance dispatching method is devised by incorporating a deadlock-avoidance strategy into a dispatching procedure that contains four sub-problems.In this strategy,critical tasks are recognized according to the status of workstation buffers,and then temporarily forbidden to avoid potential deadlocks.Secondly,three multiattribute dispatching rules are designed for system efficiency,where both the traveling distance and the buffer status are taken into account.Finally,a simulation system is developed to evaluate the performance of the proposed deadlock-avoidance strategy and dispatching rules at different NJIS levels.The experimental results demonstrate that our deadlock-avoidance dispatching method can improve the system efficiency at a high NJIS level and the adaptability to various system settings,while still avoiding potential deadlocks.
文摘芯粒集成逐渐成为不同场景下敏捷定制深度学习芯片的高可扩展性的解决方案,芯片设计者可以通过集成设计、验证完成的第三方芯粒来降低芯片开发周期和成本,提高芯片设计的灵活性和芯片良率.在传统的芯片设计和商业模式中,编译器等专用软件工具链是芯片解决方案的组成部分,并在芯片性能和开发中发挥重要作用.然而,当使用第三方芯粒进行芯片敏捷定制时,第三方芯粒所提供的专用工具链无法预知整个芯片的资源,因此无法解决敏捷定制的深度学习芯片的任务部署问题,而为敏捷定制的芯片设计全新的工具链需要大量的时间成本,失去了芯片敏捷定制的优势.因此,提出一种面向深度学习集成芯片的可扩展框架(scalable framework for integrated deep learning chips)--Puzzle,它包含从处理任务输入到运行时管理芯片资源的完整流程,并自适应地生成高效的任务调度和资源分配方案,降低冗余访存和芯粒间通信开销.实验结果表明,该可扩展框架为深度学习集成芯片生成的任务部署方案可自适应于不同的工作负载和硬件资源配置,与现有方法相比平均降低27.5%的工作负载运行延迟.
