Highly efficient class-F power amplifier with digital predistortion for WCDMA applications

A digital predistorted class-F power amplifier （PA） using Cree GaN HEMT CGH40010 operating at 2. 12 GHz is presented to obtain high efficiency and excellent linearity for wideband code-division multiple access （ WCDMA ） applications. Measurement results with the continuous wave （CW） signals indicate that the designed class-F PA achieves a peak power-added efficiency （PAE） of 75. 2% with an output power of 39.4 dBm. The adjacent channel power ratio （ACPR） of the designed PA after digital predistortion （DPD） decreases from -28. 3 and -27. 5 dBc to -51.9 and -54. 0 dBc, respectively, for a 4-carrier 20 MHz WCDMA signal with 7. 1 dB peak to average power ratio （PAPR）. The drain efficiency （DE） of the PA is 37. 8% at an average output power of 33. 3 dBm. The designed power amplifier can be aoolied in the WCDMA system.

ANALOG PREDISTORTION LINEARIZER ON REDUCING CORRECTED AMPLITUDE OVERSHOOT

This paper presents a dual-nonlinear branch linearizer for reducing the corrected amplitude overshoot of conventional single nonlinear branch linearizer. Theoretical analysis is carried out, the analysis is verified by simulation, and a prototype of Ka band 25.28~26.08 GHz dual nonlinear branch linearizer is achieved. It indicates that the corrected amplitude overshoot is less than 0.5 dB, the C/I3 improvement is more than 10 dB related to a single carrier IBO 9 dB, when it is linked and tested for 50 W spacebrone Travelling Wave Tube Amplifier(TWTA).

Adaptive Digital Predistortion Schemes to Linearize RF Power Amplifiers with Memory Effects

To compensate for nonlinear distortion introduced by RF power amplifiers （PAs） with memory effects, two correlated models, namely an extended memory polynomial （EMP） model and a memory lookup table （LUT） model, are proposed for predistorter design. Two adaptive digital predistortion （ADPD） schemes with indirect learning architecture are presented. One adopts the EMP model and the recursive least square （RLS） algorithm, and the other utilizes the memory LUT model and the least mean square （LMS） algorithm. Simulation results demonstrate that the EMP-based ADPD yields the best linearization performance in terms of suppressing spectral regrowth. It is also shown that the ADPD based on memory LUT makes optimum tradeoff between performance and computational complexity.

Wavelet network based predistortion method for wideband RF power amplifiers exhibiting memory effects

RF power amplifiers (PAs) are usually considered as memoryless devices in most existing predistortion techniques. Nevertheless, in wideband communication systems, PA memory effects can no longer be ignored and memoryless predistortion cannot linearize PAs effectively. After analyzing PA memory effects, a novel predistortion method based on wavelet networks (WNs) is proposed to linearize wideband RF power amplifiers. A complex wavelet network with tapped delay lines is applied to construct the predistorter and then a complex backpropagation algorithm is developed to train the predistorter parameters. The simulation results show that compared with the previously published feed-forward neural network predistortion method, the proposed method provides faster convergence rate and better performance in reducing out-of-band spectral regrowth.

Robust Digital Predistortion for LTE/5G Power Amplifiers Utilizing Negative Feedback Iteration

A robust digital predistortion(DPD)technique utilizing negative feedback iteration is introduced for linearizing power amplifiers(PAs)in long term evolution(LTE)/5G systems.Different from the conventional direct learning and indirect learning structure,the proposed DPD suggests a two-step method to identify the predistortion.Firstly,a negative feedback based iteration is used to estimate the optimal DPD signal.Then the corresponding DPD parameters are extracted by forward modeling with the input signal and optimal DPD signal.The iteration can be applied to both single-band and dual-band PAs,which will achieve superior linear performance than the conventional direct learning DPD while having a relatively low computational complexity.The measurement is carried out on a broadband Doherty PA(DPA)with a 200 MHz bandwidth LTE signal at 2.1 GHz,and on a 5G DPA with two 10 MHz LTE signals at 3.4/3.6 GHz for validation in dual-band scenarios.

Volterra series based predistortion for broadband RF power amplifiers with memory effects

RF power amplifiers （PAs） are usually considered as memoryless devices in most existing predistortion techniques. However, in broadband communication systems, such as WCDMA, the PA memory effects are significant, and memoryless predistortion cannot linearize the PAs effectively. After analyzing the PA memory effects, a novel predistortion method based on the simplified Volterra series is proposed to linearize broadband RF PAs with memory effects. The indirect learning architecture is adopted to design the predistortion scheme and the reeursive least squares algorithm with forgetting factor is applied to identify the parameters of the predistorter. Simulation results show that the proposed predistortion method can compensate the nonlinear distortion and memory effects of broadband RF PAs effectively.

Digital Predistortion and Measurement Method

Digital PreDistortion(DPD)is a very useful method to improve the linearity of Power Amplifiers(PAs)for LTE and upcoming 5 G networks.As the spectrum resources are becoming more and more crowded,and the communications bandwidth are broader,the ACPR(Adjacent Channel Leakage Ratio)is very important to communication systems.DPD is one of the useful means for PA to reduce ACPR.This article demonstrates what DPD is and how DPD is achieved,the measurement of the Digital Distortion of a PA using a vector generator and vector analyzer,and the measurement results has been discussed.

A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System

At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency （RF） power amplifier system is reducing its complexity of engineering realization and improving anti-jamming ability and computational speed. Besides, opening up its application scope should be contained. For these targets, a novel method including integer loop delay estimation and fractional part is proposed. The integer part applies amplitude-difference summation function and the fractional one adopts the method of finite impulse response （FIR） linear interpolation. The algorithm finds wide applications. What is more, strong anti-jamming ability and low complexity are also its merits. Simulation results support the above opinion. Digital predistortion （DPD） system based on this algorithm achieves good performance.

A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave.It adopts a three-stage single-ended structure at 28GHz.An analog predistortion lmearization method is used to improve the linearity of the power amplifier(PA).As a result,there is a significant improvement in power-added efficiency(PAE)and linearity is achieved.The Ka-band PA is implemented in TSMC 65nm CMOS process.At 1.2V supply voltage,the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%.After linearization,the output power at the ldB compression point is increased by 2dBm,with efficient gain compensation performance.

Step memory polynomial predistorter for power amplifiers with memory

To reduce the number of digital predistortion coefficients, a step memory polynomial （SMP）predistorter is presented. The number of predistortion coefficients is decreased by adjusting the maximum nonlinear order for different memory orders in the traditional memory polynomial （MP）predistorter. The proposed SNIP predistorter is identified by an offline learning structure on which the coefficients can be extracted directly from the sampled input and output of a PA. Simulation results show that the SMP predistorter is not tied to a particular PA model and is, therefore, robust. The effectiveness of the SMP predistorter is demonstrated by simulations and experiments on an MP model, a parallel Wiener model, a Wiener-Hammerstein model, a sparsedelay memory polynomial model and a real PA which is fabricated based on the Freescale LDMOSFET MRF21030. Compared with the traditional MP predistorter, the SMP predistorter can reduce the number of coefficients by 60%.

Design of a memory polynomial predistorter for wideband envelope tracking amplifiers

Efficiency and linearity of the microwave power amplifier are critical elements for mobile communication systems. A memory polynomial baseband predistorter based on an indirect learning architecture is presented for improving the linearity of an envelope tracing （ET） amplifier with application to a wireless transmitter. To deal with large peak-to-average ratio （PAR） problem, a clipping procedure for the input signal is employed. Then the system performance is verified by simulation results. For a single carrier wideband code division multiple access （WCDMA） signal of 16-quadrature amplitude modulation （16-QAM）, about 2% improvement of the error vector magnitude （EVM） is achieved at an average output power of 45.5 dBm and gain of 10.6 dB, with adjacent channel leakage ratio （ACLR） of -64.55 dBc at offset frequency of 5 MHz. Moreover, a three-carrier WCDMA signal and a third-generation （3G） long term evolution （LTE） signal are used as test signals to demonstrate the performance of the proposed linearization scheme under different bandwidth signals.

Robust power amplifier predistorter by using memory polynomials

In memory polynomial predistorter design, the coefficient estimation algorithm based on normalized least mean square is sensitive to initialization parameters. A predistorter based on generalized normalized gradient descent algorithm is proposed. The merit of the GNGD algorithm is that its learning rate provides compensation for the independent assumptions in the derivation of NLMS, thus its stability is improved. Computer simulation shows that the proposed predistorter is very robust. It can overcome the sensitivity of initialization parameters and get a better linearization performance.

A Discrete Newton's Method for Gain Based Predistorter

Gain based predistorter (PD) is a highly effective and simple digital baseband predistorter which compensates for the nonlinear distortion of PAs. Lookup table (LUT) is the core of the gain based PD. This paper presents a discrete Newton’s method based adaptive technique to modify LUT. We simplify and convert the hardship of adaptive updating LUT to the roots finding problem for a system of two element real equations on athematics. And we deduce discrete Newton’s method based adaptive iterative formula used for updating LUT. The iterative formula of the proposed method is in real number field, but secant method previously published is in complex number field. So the proposed method reduces the number of real multiplications and is implemented with ease by hardware. Furthermore, computer simulation results verify gain based PD using discrete Newton’s method could rectify nonlinear distortion and improve system performance. Also, the simulation results reveal the proposed method reaches to the stable statement in fewer iteration times and less runtime than secant method.

Realization of a tunable analog predistorter using parallel combination technique for laser driver applications

This paper describes a new approach for designing analog predistorters that can compensate for the nonlinear distortion of laser drivers in a radio-over-fiber （RoF） system. In contrast to previous works, this paper analyzes the transfer characteristics of CMOS transistors, by combining parallel currents of CMOS transistors in various W/L and negative bias voltages to realize the tunable analog predistortion function. The circuit is fabricated by a standard 0.18txm CMOS technology. The core circuit current consumption is only 15mA and the entire driver circuit works in a band-pass from 1 - 2.2GHz. Experimental results of two-tone tests have shown that with an analog predistortoer the IIP3 of the laser driver circuit has an improvement of 4.91 dB.

A dynamic coefficient polynomial predistorter based on direct learning architecture

A dynamic coefficient polynomial predistorter based on direct learning architecture is proposed.Compared to the existing polynomial predistorter,on the one hand,the proposed predistorter based on thedirect learning architecture is more robust to initial conditions of the tap coefficients than that based on in-direct learning architecture;on the other hand,by using two polynomial coefficient combinations,differ-ent polynomial coefficient combination can be selected when the input signal amplitude changes,whicheffectively decreases the estimate error.This paper introduces the direct learning architecture and givesthe dynamic coefficient polynomial expression.A simplified nonlinear recursive least-squares(RLS)algo-rithm for polynomial coefficient estimation is also derived in detail.Computer simulations show that theproposed predistorter can attain 31 dB,28dB and 40dB spectrum suppression gain when our method is ap-plied to the traveling wave tube amplifier(TWTA),solid state power amplifier(SSPA)and polynomialpower amplifier(PA)model,respectively.

数字预失真系统整数时延估计方法研究

在数字预失真系统中,相关检测法是常用的时延估计算法。为了降低相关函数对噪声的敏感度,减少数字预失真系统时间延迟估计误差,将希尔伯特差值法和不同加权函数的广义相关时延估计算法相结合,并通过仿真比较,选取时延估计性能较好的基于CC(cross correlation)加权的广义相关希尔伯特差值算法用于数字预失真系统的整数时延估计。仿真结果表明:基于CC加权的广义相关希尔伯特差值算法用时较少,受噪声影响较小,时延估计性能较好,能有效降低时间延迟估计误差,提高系统性能,有利于实际应用。

Ku波段800 W氮化镓高线性固态功放研制

介绍了一种Ku波段800 W氮化镓(GaN)高线性度固态功放的工程实现。使用32片GaN功率芯片,采用微带Gysel功分器与波导功分/合成网络相结合的方式进行功率合成,功放在750 MHz的工作频带内连续波饱和输出功率大于850 W。采用射频预失真线性化技术优化氮化镓功放线性度,功放三阶互调指标改善幅度大于5 dB,优于-32 dBc。功放选择带热管的翅片散热器的强制风冷方案,提高了散热器的换热效率,散热性能良好。通过实时监测功放芯片管壳温度,自动配置散热风扇转速,实现了功放的自适应热管理,在降低功放功耗的同时,减小了产品噪声。功放配置了完善的控保功能,技术状态稳定。由两台功放组成了1备1组件系统,可靠性及实用性满足工程使用要求,适用于测控、通信、广电等领域的微波发射系统。

C波段2000 W氮化镓线性固态功放研制

介绍了一种C波段2000 W氮化镓高功率线性固态功放的工程实现。使用32片GaN功率管芯芯片,采用微带Gysel功分器与波导功分/合成网络相结合的方式进行功率合成,功放在900 MHz的工作频带内连续波饱和输出功率大于2000 W,最大输出功率2290 W。采用射频预失真线性化技术优化氮化镓功放线性度,功放三阶互调指标改善幅度大于4 dB,优于-29 dBc。选择带热管的翅片散热器的强制风冷方案,提高散热器的换热效率,散热性能良好。功放配置了完善的控保功能,可靠性及实用性满足工程使用要求。功放插箱和电源模块采用热插拔设计,便于快速维修,适用于测控、通信、广电等领域的微波发射系统。

调制解调非理想特性联合补偿数字预失真方法

针对调制解调非理想特性影响数字预失真效果,导致邻信道功率比性能较差的问题,提出了一种调制端和解调端联合补偿的数字预失真方法。首先,建立了正交调制器、解调器的基带等效模型;然后,基于多项式预失真,利用正交调制器与解调器的特点,结合递归最小二乘法,推导出了联合补偿数字预失真原理,避免了仅通过调制端补偿,或者调制端、解调端分别补偿只能使数字预失真算法收敛到局部最优解的现象出现;最后,以甚高频航空通信常用的差分八相移键控(Differential 8 Phase Shift Keying,D8PSK)调制方式为例进行了仿真和实现验证,邻信道功率比相对无预失真可以改善28 dBc,相对现有联合补偿数字预失真可以改善16 dBc。

面向高阶调制的5G宽带射频功放数字预失真技术

在第5代无线通信系统(5G)中,射频(RF)功放(PAs)有着严重的非线性失真和强记忆效应,尤其是对于采用复杂的高阶调制系统,如16QAM、64QAM等。为了研究和提高宽带RF PAs的线性化能力,提出基于先进设计系统(advanced design system,ADS)设计的宽带RF PAs,工作的中心频率为3.55 GHz,采用记忆多项式(MP)模型构建数字预失真器,模型的归一化均方误差(NMSE)指标可达-33.28 d B。最后,采用带宽为100 MHz的16QAM或64QAM高阶调制的5G新空口(new radio,NR)信号,信号最大幅度值为9.899 d B,对中心频率为3.55 GHz的RF PAs进行预失真仿真验证。仿真结果表明,在16QAM调制方式下,邻信道功率比(ACPR)可分别改善20.13 dB和20.05 dB;在64QAM调制方式下,ACPR可分别改善18.35 dB和19.08 dB。实验测试结果表明,在16QAM调制方式下,ACPR分别改善15.81 dB和16.40 dB;在64QAM调制方式下,ACPR分别改善15.44 dB和15.82 dB。说明基于MP的数字预失真器对基于ADS的RF PAs的非线性具有明显的抑制作用。因此基于MP模型的数字预失真器可用于所提RF PAs的线性化,且采用16QAM调制方式比基于64QAM调制方式的预失真能力更强。