Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% o...Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.展开更多
提出了一种高温 SOI CMOS电路设计方法—自动体偏置多阈值电压 SOI CMOS(简称 ABB－MT－ SOI CMOS： Auto－ Bulk－ Biased Multi－ Threshold SOI CMOS)电路。文中主要讨论了 ABB－MT－ SOI CMOS电路的结构与工作原理 ,设计与布局等，...提出了一种高温 SOI CMOS电路设计方法—自动体偏置多阈值电压 SOI CMOS(简称 ABB－MT－ SOI CMOS： Auto－ Bulk－ Biased Multi－ Threshold SOI CMOS)电路。文中主要讨论了 ABB－MT－ SOI CMOS电路的结构与工作原理 ,设计与布局等，给出了内部电路电压和电流的模拟结果，并简述了该电路的应用前景。展开更多
文摘Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.
文摘提出了一种高温 SOI CMOS电路设计方法—自动体偏置多阈值电压 SOI CMOS(简称 ABB－MT－ SOI CMOS： Auto－ Bulk－ Biased Multi－ Threshold SOI CMOS)电路。文中主要讨论了 ABB－MT－ SOI CMOS电路的结构与工作原理 ,设计与布局等，给出了内部电路电压和电流的模拟结果，并简述了该电路的应用前景。
