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Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits
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作者 C.Arun Prasath C.Gowri Shankar 《Intelligent Automation & Soft Computing》 SCIE 2023年第2期1767-1781,共15页
Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel... Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel Metal Oxide Semiconductor(PMOS)has been replaced by Negative Channel Metal Oxide Semiconductor(NMOS)in recent years,with low dimen-sion-switching changes in order to shape the mirror of voltage comparator.NMOS is used to reduce stacking leakage as well as total exchange.Domino Logic Cir-cuit is a powerful and versatile digital programmer that gained popularity in recent years.In this study regarding Adaptive Sub Threshold Voltage Level Control Pro-blem,the researchers intend to solve the contention issues,reduce power dissipa-tion,and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control(ASVLC)-based domino circuit.The efficiency and effec-tiveness of the domino circuit are demonstrated through simulation results.The suggested system makes use of high-speed broad fan-gate circuits,occupies mini-mum space,and consumes meagre amount of power.The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V,frequency of 100 MHz,and an operating temperature of 27°C with 64 input OR gates.As per the simulation results,the suggested Domino Gate reduced the power dissipa-tion by 17.58 percent and improved the noise immunity by 1.21 times in compar-ison with standard domino logic circuits. 展开更多
关键词 Domino logic power consumption figure of merit adaptive sub-threshold voltage level wide fan-in gates
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高能效宽电压工作标准单元库分析与优化
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作者 王京睿 李翔宇 《微电子学与计算机》 CSCD 北大核心 2016年第8期72-75,共4页
研究了剔除大扇入逻辑门对于高电源电压下的电路指标的影响,证实这一方法对电路在高电压下的性能和功耗没有明显的负面影响,主要影响是在一定程度上增大电路的面积.分别对32nm标准单元库中的异步置位复位D触发器单元和电平移位器单元进... 研究了剔除大扇入逻辑门对于高电源电压下的电路指标的影响,证实这一方法对电路在高电压下的性能和功耗没有明显的负面影响,主要影响是在一定程度上增大电路的面积.分别对32nm标准单元库中的异步置位复位D触发器单元和电平移位器单元进行了电路优化,使得它们在低电压下的延时分别减少了14.6%和19.9%,解决了电源电压降至近阈值时性能恶化过于严重的问题. 展开更多
关键词 能量效率 近阈值 宽电压工作 大扇入逻辑门 D触发器 电平移位器
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