Enhanced thermoelectric performance in Ga_(x)Co_(4)Sb_(12.3-y)Te_(y) skutterudites via suppressing bipolar effects for commercial application

The n-type filled and doped skutterudites Ga_(x)Co_(4)Sb_(12.3) and Ga_(0.2)Co_(4)Sb_(11.3)Te composites with the welldistributed GaSb nanoinclusions are synthesized through the manipulating of metastable Ga fillers and enrichment of Sb by an in-situ method with a proper annealing procedure.Ga atoms can fill the icosahedron cages of skutterudite at high temperature,but at low temperature,they are driven out from the lattice voids and form the second phase of GaSb at grain boundaries.The presence of GaSb second phases reduces the thermal conductivity effectively.Te doping leads to a significant increase in carrier concentration of Ga_(0.2)Co_(4)Sb_(11.3)Te,thus largely suppresses the bipolar effect of Ga_(x)Co_(4)Sb_(12.3),resulting in a great enhancement in power factor.Moreover,Te doping induces mass and strain fluctuation,which decreases the lattice thermal conductivity further.Consequently,the maximum ZT is increased from 0.56 for Ga_(0.2)Co_(4)Sb_(12.3) at 573 K to 1.48 for Ga_(0.2)Co_(4)Sb_(11.3)Te at 873 K,which is advantageous to improve the thermoelectric conversion efficiency for commercial application.

New insight into the parasitic bipolar amplification effect in single event transient production

In this paper, a new method is proposed to study the mechanism of charge collection in single event transient （SET） production in 90 nm bulk complementary metal oxide semiconductor （CMOS） technology. We find that different from the case in the pMOSFET, the parasitic bipolar amplification effect （bipolar effect） in the balanced inverter does not exist in the nMOSFET after the ion striking. The influence of the suhstrate process on the bipolar effect is also studied in the pMOSFET. We find that the bipolar effect can be effectively mitigated by a buried deep P＋-well layer and can be removed by a buried SO2 layer.

Improved high-frequency equivalent circuit model based on distributed effects for SiGe HBTs with CBE layout

In this paper, we present an improved high-frequency equivalent circuit for SiGe heterojunction bipolar transistors（HBTs） with a CBE layout, where we consider the distributed effects along the base region. The actual device structure is divided into three parts： a link base region under a spacer oxide, an intrinsic transistor region under the emitter window,and an extrinsic base region. Each region is considered as a two-port network, and is composed of a distributed resistance and capacitance. We solve the admittance parameters by solving the transmission-line equation. Then, we obtain the smallsignal equivalent circuit depending on the reasonable approximations. Unlike previous compact models, in our proposed model, we introduce an additional internal base node, and the intrinsic base resistance is shifted into this internal base node,which can theoretically explain the anomalous change in the intrinsic bias-dependent collector resistance in the conventional compact model.

Temperature dependence of the P-hit single event transient pulse width in a three-transistor inverter chain

A comparison of the temperature dependence of the P-hit single event transient （SET） in a two-transistor （2T） inverter with that in a three-transistor （3T） inverter is carried out based on a three-dimensional numerical simulation. Due to the significantly distinct mechanisms of the single event change collection in the 2T and the 3T inverters, the temperature plays different roles in the SET production and propagation. The SET pulse will be significantly broadened in the 2T inverter chain while will be compressed in the 3T inverter chain as temperature increases. The investigation provides a new insight into the SET mitigation under the extreme environment, where both the high temperature and the single event effects should be considered. The 3T inverter layout structure （or similar layout structures） will be a better solution for spaceborne integrated circuit design for extreme environments.

Inhibiting the bipolar effect via band gap engineering to improve the thermoelectric performance in n-type Bi_(2-x)Sb_(x)Te_(3)for solid-state refrigeration

To date,the benchmark Bi_(2)Te_(3)-based alloys are still the only commercial material system used for ther-moelectric solid-state refrigeration.Nonetheless,the conspicuous performance imbalance between the p-type Bi_(2-x)Sb_(x)Te_(3)and n-type Bi_(2)Te_(3-x)Se_(x) legs has become a major obstacle for the improvement of cooling devices to achieve higher efficiency.In our previous study,novel n-type Bi_(2-x)Sb_(x)Te_(3)alloy has been pro-posed via manipulating donor-like effect as an alternative to mainstream n-type Bi_(2)Te_(3-x)Se_(x).However,the narrow bandgap of Bi_(2-x)Sb_(x)Te_(3)provoked severe bipolar effect that constrained the further improvement of zT near room temperature.Herein,we have implemented band gap engineering in n-type Bi_(1.5)Sb_(0.5)Te_(3)by employing isovalent Se substitution to inhibit the undesired intrinsic excitation and achieve the dis-tinguished room-temperature zT.First,the preferential occupancy of Se at Te^(2)site appropriately enlarges the band gap,thereby concurrently improving the Seebeck coefficient and depressing the bipolar thermal conductivity.In addition,the Se alloying mildly suppresses the compensation mechanism and essentially preserves the already optimized carrier concentration,which maintains the peak zT near room tempera-ture.Moreover,the large strain field and mass fluctuation generated by Se alloying leads to the remark-able reduction of lattice thermal conductivity.Accordingly,the zT value of Bi_(1.5)Sb_(0.5)Te_(2.8)Se_(0.2)reaches 1.0 at 300 K and peaks 1.1 at 360 K,which surpasses that of most well-known room-temperature n-type thermoelectric materials.These results pave the way for n-type Bi_(2-x)Sb_(x)Te_(3)alloys to become a new and promising top candidate for large-scale solid-state cooling applications.

Enhanced thermoelectric performance through homogenously dispersed MnTe nanoparticles in p-type Bi_(0.52)Sb_(1.48)Te_3 nanocomposites

In this work,we report that the thermoelectric properties of Bi（0.52）Sb（1.48）Te3alloy can be enhanced by being composited with Mn Te nano particles（NPs）through a combined ball milling and spark plasma sintering（SPS）process.The addition of Mn Te into the host can synergistically reduce the lattice thermal conductivity by increasing the interface phononscattering between Bi（0.52）Sb（1.48）Te3 and MnTe NPs,and enhance the electrical transport properties by optimizing the hole concentration through partial Mn^2＋ acceptor doping on the Bi^3＋ sites of the host lattice.It is observed that the lattice thermal conductivity decreases with increasing the percentage of Mn Te and milling time in a temperature range from 300 Kto 500 K,which is consistent with the increasing of interfaces.Meanwhile,the bipolar effect is constrained to high temperatures,which results in the figure of merit z T peak shifting toward higher temperature and broadening the z T curves.The engineering z T is obtained to be 20%higher than that of the pristine sample for the 2-mol%Mn Te-added composite at a temperature gradient of 200 K when the cold end temperature is set to be 300 K.This result indicates that the thermoelectric performance of Bi0.52Sb1.48Te3 can be considerably enhanced by being composited with Mn Te NPs.

Experimental characterization of the bipolar effect on P-hit single-event transients in 65 nm twin-well and triple-well CMOS technologies

Single-event charge collection is controlled by drift, diffusion and the bipolar effect. Previous work has established that the bipolar effect is significant in the p-type metal-oxide-semiconductor field-effect transistor(PMOS) in 90 nm technology and above. However, the consequences of the bipolar effect on P-hit single-event transients have still not completely been characterized in 65 nm technology. In this paper, characterization of the consequences of the bipolar effect on P-hit single-event transients is performed by heavy ion experiments in both 65 nm twin-well and triple-well complementary metal-oxide-semiconductor(CMOS) technologies. Two inverter chains with clever layout structures are explored for the characterization. Ge(linear energy transfer(LET) = 37.4 Me V cm^2/mg) and Ti(LET = 22.2 Me V cm^2/mg) particles are also employed. The experimental results show that with Ge(Ti) exposure, the average pulse reduction is 49 ps(45 ps) in triple-well CMOS technology and 42 ps(32 ps) in twin-well CMOS technology when the bipolar effect is efficiently mitigated. This characterization will provide an important reference for radiation hardening integrated circuit design.

Simulation analysis of heavy-ion-induced single-event response for nanoscale bulk-Si FinFETs and conventional planar devices

FinFET technologies are becoming the mainstream process as technology scales down.Based on 28-nm bulk-Si FinFETs and

Single event transient pulse attenuation effect in three-transistor inverter chain

In this paper, compared with two-transistor (2T) inverter chain, the production and propagation of P-hit single event transient (SET) in three-transistor (3T) inverter chain is studied in depth based on three-dimensional numerical simulations in a 90 nm bulk complementary metal oxide semiconductor (CMOS) technology. The pulse attenuation effect is found in 3T inverter chain, and the pulse can not completely propagate through the inverter chain as LET increases. The discovery will provide a new insight into SET hardened design, the 3T inverter layout structure (or similar layout structures) will be a better method in integrated circuits (ICs) design in radiation environment.