This paper presents a power factor corrected (PFC) new bridgeless (BL) Cuk Topologies for low power applications. A BL configuration of Cuk converter is proposed which eliminates the usage of diode bridge rectifier at...This paper presents a power factor corrected (PFC) new bridgeless (BL) Cuk Topologies for low power applications. A BL configuration of Cuk converter is proposed which eliminates the usage of diode bridge rectifier at the front end of the PFC converter, thus reducing the switching and conduction losses coupled with it. This new BL Cuk converter has two semiconductors switches. The current flow during each switching cycle interval of the converter reduces the conduction losses compared to the conventional Cuk PFC converter. It also reduces the input current ripple and Electromagnetic Interference (EMI). The inrush current during the starting period is limited and the input, output currents of the converter are continuous with minimum current ripple. Hence it is preferred mostly compared to other PFC circuits. The proposed topology works in the Discontinuous Conduction Mode (DCM) with simple control circuitry to achieve almost a unity power factor with less distortion in the input AC current. The switching of the power switches is done under zero current. The proposed PFC topologies are theoretically investigated and performance comparisons are made with the conventional rectifiers. The proposed PFC converter is simulated in MATLAB/SIMULINK with Fuzzy Logic Controller (FLC) and results are demonstrated to evaluate the effectiveness of the controller.展开更多
In this study,a type of multilevel flying capacitor bridgeless PFC converter is proposed that permits the use of economical and efficient 100 V GaN transistors.Compared with the popular two-level totem-pole bridgeless...In this study,a type of multilevel flying capacitor bridgeless PFC converter is proposed that permits the use of economical and efficient 100 V GaN transistors.Compared with the popular two-level totem-pole bridgeless PFC converters achieved using the much more expensive 650 V GaN devices,this new design has several distinct advantages:lower component costs,lower dv/dt,lower power losses,and reduced concerns about device reliability.A 1.6 kW,5-level PFC converter prototype is designed and fabricated with an efficiency of 99.18%and a power factor of 0.99,which are experimentally demonstrated.The operation principle,design considerations,control strategy and experimental results are discussed.展开更多
The Power Factor Correction(PFC)in Switched Reluctance(SR)motor is discussed in this article.The SR motors are applicable for multiple applications like electric vehicles,wind mills,machineries etc.The doubly salient ...The Power Factor Correction(PFC)in Switched Reluctance(SR)motor is discussed in this article.The SR motors are applicable for multiple applications like electric vehicles,wind mills,machineries etc.The doubly salient structure of SR motor causes the occurrence of torque ripples,which affects the power factor of the motor.To improve the power quality,the power factor has to be corrected and the ripples have to be minimized.In order to achieve these objectives,a novel power factor correction(PFC)method is proposed in this work.Here,the conventional Diode Bridge Rectifier(DBR)is replaced by a Bridgeless Hybrid Resonant(HR)converter,which assists in improvising the output in a wider range.The converter is chosen because of having variety of beneficial measures including high gain.The converter’s output is fed to the SR motor by means of an asymmetric Bridge Resonant(BR)converter.The proposed converter operates in continuous mode of conduction with the switching frequency of 10 KHz.A hysteresis current controller and Proportional Integral(PI)controller are utilized for reducing the harmonics in the source current along with the regulation of output voltage.In addition,the speed control of SR motor is accomplished by means of the Whale Optimization Algorithm(WOA)assisted PI controller.The proposed methodology is effective for the control of unity power factor,torque and current ripples.The Total Harmonic Distortion(THD)of the source current is also minimized,which suits the standard of International Electrotechnical Comission IEC 61000-3-2.By this methodology,the power factor of 0.99 is achieved with 97%efficiency and 3.92%THD.The proposed methodology is validated in simulation by MATLAB and in hardware by FPGA Spartan 6E.展开更多
文摘This paper presents a power factor corrected (PFC) new bridgeless (BL) Cuk Topologies for low power applications. A BL configuration of Cuk converter is proposed which eliminates the usage of diode bridge rectifier at the front end of the PFC converter, thus reducing the switching and conduction losses coupled with it. This new BL Cuk converter has two semiconductors switches. The current flow during each switching cycle interval of the converter reduces the conduction losses compared to the conventional Cuk PFC converter. It also reduces the input current ripple and Electromagnetic Interference (EMI). The inrush current during the starting period is limited and the input, output currents of the converter are continuous with minimum current ripple. Hence it is preferred mostly compared to other PFC circuits. The proposed topology works in the Discontinuous Conduction Mode (DCM) with simple control circuitry to achieve almost a unity power factor with less distortion in the input AC current. The switching of the power switches is done under zero current. The proposed PFC topologies are theoretically investigated and performance comparisons are made with the conventional rectifiers. The proposed PFC converter is simulated in MATLAB/SIMULINK with Fuzzy Logic Controller (FLC) and results are demonstrated to evaluate the effectiveness of the controller.
基金Supported by the National Natural Science Foundation of China(51977068).
文摘In this study,a type of multilevel flying capacitor bridgeless PFC converter is proposed that permits the use of economical and efficient 100 V GaN transistors.Compared with the popular two-level totem-pole bridgeless PFC converters achieved using the much more expensive 650 V GaN devices,this new design has several distinct advantages:lower component costs,lower dv/dt,lower power losses,and reduced concerns about device reliability.A 1.6 kW,5-level PFC converter prototype is designed and fabricated with an efficiency of 99.18%and a power factor of 0.99,which are experimentally demonstrated.The operation principle,design considerations,control strategy and experimental results are discussed.
文摘The Power Factor Correction(PFC)in Switched Reluctance(SR)motor is discussed in this article.The SR motors are applicable for multiple applications like electric vehicles,wind mills,machineries etc.The doubly salient structure of SR motor causes the occurrence of torque ripples,which affects the power factor of the motor.To improve the power quality,the power factor has to be corrected and the ripples have to be minimized.In order to achieve these objectives,a novel power factor correction(PFC)method is proposed in this work.Here,the conventional Diode Bridge Rectifier(DBR)is replaced by a Bridgeless Hybrid Resonant(HR)converter,which assists in improvising the output in a wider range.The converter is chosen because of having variety of beneficial measures including high gain.The converter’s output is fed to the SR motor by means of an asymmetric Bridge Resonant(BR)converter.The proposed converter operates in continuous mode of conduction with the switching frequency of 10 KHz.A hysteresis current controller and Proportional Integral(PI)controller are utilized for reducing the harmonics in the source current along with the regulation of output voltage.In addition,the speed control of SR motor is accomplished by means of the Whale Optimization Algorithm(WOA)assisted PI controller.The proposed methodology is effective for the control of unity power factor,torque and current ripples.The Total Harmonic Distortion(THD)of the source current is also minimized,which suits the standard of International Electrotechnical Comission IEC 61000-3-2.By this methodology,the power factor of 0.99 is achieved with 97%efficiency and 3.92%THD.The proposed methodology is validated in simulation by MATLAB and in hardware by FPGA Spartan 6E.