VST/DL Digital Circuit Testing & Analytical System

An important means for digital circuit analysis, design. maintenance and production is the IC chip test and analysis. With digital circuit application prevailing today, the automatic test and analysis of digital circuits is going to play a more important role. It can save a great deal of time and cost for the maintenance of equipment and can also provide correst analytical data for designers.

Chair's Introduction to 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis

Based on the recommendation of ICTD＇09 TPC members, this Special Issue of the Journal of Electronic Science ＆ Technology of China （JESTC） contained 22 high quality papers selected from the Proceedings of 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis （ICTD ＇09） which is fully sponsored by the IEEE Circuits and Systems Society （CASS）, and is technically co-sponsored by the University of Electronic Science and Technology of China （UESTC）, the Chinese Institute of Electronics （CIE）, the China Instrument ＆ Control Society （CIS）, and organized by UESTC.

test252 kV三相机械联动GIS用断路器的T100s合并试验

交流高压断路器标准GB/T 1984—2014中规定了中性点有效和非有效接地系统的合并试验,但是不涉及60Hz的工况,对应STL导则中针对IEC 62271-100有50/60Hz合并试验的描述,但是国内厂家50/60Hz通常是分开试验的。文章通过介绍252kV断路器T100s的多参数的合并试验,提供了一种可以多参数试验的试验方法,指出了多参数合并试验的利弊,对后续其他类似多参数合并试验提供了有效参考。

A Radial Stub Test Circuit for Microwave Power Devices

With the principles of microwave circuits and semiconductor device physics, two microwave power device test circuits combined with a test fixture are designed and simulated, whose properties are evaluated by a parameter network analyzer within the frequency range from 3 to 8GHz. The simulation and experimental results verify that the test circuit with a radial stub is better than that without. As an example, a C-band AlGaN/GaN HEMT microwave power device is tested with the designed circuit and fixture. With a 5.4GHz microwave input signal,the maximum gain is 8.75dB,and the maximum output power is 33.2dBm.

The Transformer Short-Circuit Test and the High Power Laboratory in China-the Past,Present,and Future

We review the short-circuit testing of distribution and power transformers, and include a list of 110-220kV power transformers tested up to February 2002.

Test system of the front-end readout for an application-specific integrated circuit for the water Cherenkov detector array at the large high-altitude air shower observatory

The water Cherenkov detector array(WCDA) is an important part of the large high-altitude air shower observatory(LHAASO),which is in a research and development phase.The central scientific goal of LHAASO is to explore the origin of high-energy cosmic rays of the universe and to push forward the frontier of new physics.To simplify the WCDA's readout electronics,a prototype of a front-end readout for an application-specific integrated circuit(ASIC) is designed based on the timeover-threshold method to achieve charge-to-time conversion.High-precision time measurement and charge measurement are necessary over a full dynamic range[1-4000photoelectrons(P.E.)].To evaluate the performance of this ASIC,a test system is designed that includes the front-end ASIC test module,digitization module,and test software.The first module needs to be customized for different ASIC versions,whereas the digitization module and test software are tested for general-purpose use.In the digitization module,a field programmable gate array-based time-todigital converter is designed with a bin size of 333 ps,which also integrates an inter-integrated circuit to configure the ASIC test module,and a universal serial bus interface is designed to transfer data to the remote computer.Test results indicate that the time resolution is better than 0.5 ns,and the charge resolution is better than 30%root mean square(RMS) at 1 P.E.and 3%RMS at 4000 P.E.,which are beyond the application requirements.

Research on the overload protection reliability of moulded case circuit-breakers and its test device

This paper analyzed the reliability and put forward the reliability index of overload protection for moulded case circuit breaker. The success rate was adopted as its reliability index of overload protection. Based on the reliability index and the reli- ability level, the reliability examination plan was analyzed and a test device for the overload protection of moulded case cir- cuit-breaker was developed. In the reliability test of overload protection, two power sources were used, which reduced the time of conversion and regulation between two different test currents in the overload protection test, which made the characteristic test more accurate. The test device was designed on the base of a Windows system, which made its operation simple and friendly.

Random testing for system-level functional verification of system-on-chip

In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.

Modeling and Simulation for Complex Repairable System with Built-in Test Equipment

In order to research the effects of built-in test(BIT) on the system and select BITand test strategy,the complex repairable systems with BITequipment are modeled and simulated by using Simulink.Based on the model,the influences of different built-in test equipments,maintenance time and error probabilities on the system usability are evaluated.The simulation results showthat they effect on the system differently.The simulation method of complex system based on Simulink provides a technique approach to research the effects of BITon the system and select BITand test strategy.

Key stress extraction and equivalent test method for hybrid DC circuit breaker

Firstly, relevant stress properties of millisecond level breaking process and microsecond level commutation process of hybrid HVDC circuit breaker are studied in detail on the basis of the analysis for the application environment and topological structure and operating principles of hybrid circuit breakers, and key stress parameters in transient state process of two time dimensions are extracted. The established digital simulation circuit for PSCAD/EMTDC device-level operation of the circuit breaker has verified the stress properties of millisecond level breaking process and microsecond level commutation process. Then, equivalent test method, circuits and parameters based on LC power supply are proposed on the basis of stress extraction. Finally, the results of implemented breaking tests for complete 200 kV circuit breaker, 100 kV and 50 kV circuit breaker units, as well as single power electronic module have verified the accuracy of the simulation circuit and mathematical analysis. The result of this paper can be a guide to electrical structure and test system design of hybrid HVDC circuit breaker.

An Adaptive Ramp Generator for ADC Built-in Self-Test

An adaptive ramp generator based on linear histogram was proposed for the built-in selftest (BIST) of analog to digital convertor (ADC) in CMOS image sensor. By comparing the generated ramp signal to a reference voltage and feeding back a calibration signal, the slope adjustment was implemented, and high linearity and precision of ramp slope were realized. By modulating the pulse width and reference voltage, sweep length varied from microsecond to second and signal swing could reach 3 V with 5.6 mW power consumption. The ramp was used as input to an ideal 10-bit single-slope ADC, and the corresponding DNL and INL were 0.032 LSB and 0.078 LSB, re-spectively.

An optimal stacking order for mid-bond testing cost reduction of 3D IC

In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.

Influence of Tilted Angle on Effective Linear Energy Transfer in Single Event Effect Tests for Integrated Circuits at 130 nm Technology Node

A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.

Investigation into Equivalency of Synthetic Test Circuit Used for Operational Tests of Thyristor Valves for UHVDC

With the growth of capacity of high voltage direct current(HVDC) transmission lines,the ratings of thyristor valves,which are one of the most critical equipments,are getting higher and higher.Verification of performance of thyristor valves particularly designed for HVDC project plays an important role in the handover of products between the manufacturer and the client.Conventional test facilities based on philosophy of direct test cannot meet the requirements for modern thyristor valves.New test facilities with high ratings are necessarily built based on philosophy of synthetic test.Over the conventional direct test circuit,the later is an economical and feasible solution with less financial investment and higher test capability.However,the equivalency between the synthetic test and the direct test should be analyzed technically in order to make sure that the condition of verification test in a synthetic test circuit should satisfy the actual operation condition of thyristor valves existing in a real HVDC project,just as in a direct test circuit.Equivalency analysis is focused in this paper,covering the scope of thyristor valves' steady state,and transient state.On the basis of the results achieved,a synthetic test circuit of 6 500 A/50 kV for operational tests of thyristor valves used for up to UHVDC project has newly been set up and already put into service in Xi'an High Voltage Apparatus Research Institute Co.,Ltd.(XIHARI),China.Some of the results have been adopted also by a new national standard of China.

Research of the test generation algorithm based on search state dominance for combinational circuit

On the basis of EST (Equivalent STate hashing) algorithm, this paper researches a kind of test generation algorithm based on search state dominance for combinational circuit. According to the dominance relation of the E-frontier (evaluation frontier), we can prove that this algorithm can terminate unnecessary searching step of test pattern earlier than the EST algorithm through some examples, so this algorithm can reduce the time of test generation. The test patterns calculated can detect faults given through simulation.

The structure-based multi-fault test generation algorithm for combinational circuit

In this paper the structure-based test generation algorithm has been studied for the problem that test patterns are obtained by determined finite faults set in the past. This Algorithm can find out all test patterns one tithe, so faults detection is very convenient. By simulation, the smallest test patterns set can be obtained and faults coverage rate is 100%.

A new approach to test generation for combinational circuits

Aimed at the generation of high-quality test set in the shortest possible time, the test generation for combinational circuits （CC） based on the chaotic particle swarm optimization （CPSO） algorithm is presented according to the analysis of existent problems of CC test generation, and an appropriate CPSO algorithm model has been constructed. With the help of fault simulator, the test set of ISCAS＇ 85 benchmark CC is generated using the CPSO, and some techniques are introduced such as half-random generation, and simulation of undetected fauhs.with original test vector, and inverse test vector. Experimental results show that this algorithm can generate the same fault coverage and small-size test set in short time compared with other known similar methods, which proves that the proposed method is applicable and effective.

Hard IP Core Nondestructive Testing Technology

Based on the analysis of the existing hard IP core testing technology, the hard IP core nondestructive testing technology was studied, according to the verification requirements of a large number of hard IP core precise and fast testing. Combined with the external automatic test equipment (ATE) and the on-chip evaluation circuit, a general evaluation system of simulating user system on chip (SOC) with signal timing calibration and compensation by software and hardware compensation structures were introduced to realize the function, performance and reliability verification of the hard IP core. The design and verification of a random access memory (SRAM) hard IP core based on an on-chip evaluation circuit was actually completed, and the key timing parameters of the hard IP core were tested. The address setup time parameter was taken as an example to analyze the specific testing method and the test results were obtained. With this testing technology, the accuracy of testing the timing parameters of hard IP core can reach pS level, compared with the hard IP core packaged test, the accuracy of the result data is fully reflected.

The embedded design verification test of microwave circuit modules based on specific chips

In the Paper,the author introduces an embedded design verification test based on specific chips to solve the technical problems of microwave circuit test and fault diagnosis.The author explains embedded design of microwave circuit modules and approach of hardware design and software design,and finally verifies the embedded design of microwave circuit modules based on specific chips.

Support-Vector-Machine-Based False Alarm Filter of Mechatronic Built-in Test

Diagnosing intermittent fault is an important approach to reduce built-in test（BIT） false alarms. Aiming at solving the shortcoming of the present diagnostic method of intermittent fault, and according to the merit of support vector machines （ SVM） which can be trained with a small-sample, an SVM-based diagnostic model of 3 states that include OK state, intermittent state and faulty state is presented. With the features based on the reflection coefficients of an alarm rate （ AR ） model extracted from small vibration samples, these models are trained to diagnose intermittent faults. The experimental results show that this method can diagnose multiple intermittent faults accurately with small training samples and BIT false alarms are reduced.