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Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics 被引量:1
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作者 张德良 封常青 +9 位作者 张俊斌 王奇 马思源 沈仲弢 蒋荻 高山山 张云龙 郭建华 刘树彬 安琪 《Chinese Physics C》 SCIE CAS CSCD 2016年第5期51-57,共7页
DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for clark matter in st)ace. One critical sub-detector of the DAMPE payload is the BGO (bismuth germaniu... DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for clark matter in st)ace. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to inonitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operatioual amplifier and an analog switch. Test results showed that a dynamic range of 0- 30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160's input range. It can be used to compensate for the teinperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. 展开更多
关键词 DAMPE BGO calorimeter front-end electronics calibration circuit VA160
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A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS
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作者 贺文伟 孟桥 +1 位作者 张翼 唐凯 《Journal of Semiconductors》 EI CAS CSCD 2014年第8期140-144,共5页
A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is pre- sented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold ampli- ... A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is pre- sented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold ampli- fier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a dif- ferential nonlinearity 〈 4-0.3 LSB and an integral nonlinearity 〈 ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply. 展开更多
关键词 folding and interpolating SHA COMPARATOR foreground digital calibration circuit
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