介绍了二进制数的Canonic Signed Digit(CSD)表示的特点,0位值比其他表示方法都要多。应用这一点在常系数的乘法器中,可以化简电路。阐述了CSD串并乘法器的具体化简过程,并应用这一技术于IS95-WCDMA中的脉冲整形23阶常系数FIR的设计中,...介绍了二进制数的Canonic Signed Digit(CSD)表示的特点,0位值比其他表示方法都要多。应用这一点在常系数的乘法器中,可以化简电路。阐述了CSD串并乘法器的具体化简过程,并应用这一技术于IS95-WCDMA中的脉冲整形23阶常系数FIR的设计中,面积缩小达42%。结果表明:CSD的化简效果是明显的。展开更多
In this paper, we present a novel and efficient method for the design of a sharp, two dimensional (2D) wideband, circularly symmetric, FIR filter. First of all, a sharp one dimensional (1D) infinite precision FIR filt...In this paper, we present a novel and efficient method for the design of a sharp, two dimensional (2D) wideband, circularly symmetric, FIR filter. First of all, a sharp one dimensional (1D) infinite precision FIR filter is designed using the Frequency Response Masking (FRM) technique. This filter is converted into a multiplier-less filter by representing it in the Canonic Signed Digit (CSD) space. The design of the FRM filter in the CSD space calls for the use of a discrete optimization technique. To this end, a new optimization approach is proposed using a modified Harmony Search Algorithm (HSA). HSA is modified in such a way that, in every exploitation and exploration phase, the candidate solutions turns out to be integers. The 1D FRM multiplier-less filter, is in turn transformed to the 2D equivalent using the recently proposed multiplier-less transformations namely, T1 and T2. These transformations are successful in generating circular contours even for wideband filters. Since multipliers are the most power consuming elements in a 2D filter, the multiplier-less realization calls for reduced power consumption as well as computation time. Significant reduction in the computational complexity and computation time are the highlights of our proposed design technique. Besides, the proposed discrete optimization using modified HSA can be used to solve optimization problems in other engineering disciplines, where the search space consists of integers.展开更多
给出了一种适用于PHS基带系统中的高性能成形滤波器,对比两种实现方法在基带芯片中的性能,利用最少的非零比特位来表示符号数的编码技术即符号数(Canonic Sign D igit,CSD)。采用子结构共享技术改进数字滤波器结构,实现了2进制补码与CS...给出了一种适用于PHS基带系统中的高性能成形滤波器,对比两种实现方法在基带芯片中的性能,利用最少的非零比特位来表示符号数的编码技术即符号数(Canonic Sign D igit,CSD)。采用子结构共享技术改进数字滤波器结构,实现了2进制补码与CSD的转换和系统中升余弦Nyquist成形滤波器的ASIC设计,在TSMC 0.18μm工艺下进行了功能仿真、综合和后仿真。展开更多
文摘介绍了二进制数的Canonic Signed Digit(CSD)表示的特点,0位值比其他表示方法都要多。应用这一点在常系数的乘法器中,可以化简电路。阐述了CSD串并乘法器的具体化简过程,并应用这一技术于IS95-WCDMA中的脉冲整形23阶常系数FIR的设计中,面积缩小达42%。结果表明:CSD的化简效果是明显的。
文摘In this paper, we present a novel and efficient method for the design of a sharp, two dimensional (2D) wideband, circularly symmetric, FIR filter. First of all, a sharp one dimensional (1D) infinite precision FIR filter is designed using the Frequency Response Masking (FRM) technique. This filter is converted into a multiplier-less filter by representing it in the Canonic Signed Digit (CSD) space. The design of the FRM filter in the CSD space calls for the use of a discrete optimization technique. To this end, a new optimization approach is proposed using a modified Harmony Search Algorithm (HSA). HSA is modified in such a way that, in every exploitation and exploration phase, the candidate solutions turns out to be integers. The 1D FRM multiplier-less filter, is in turn transformed to the 2D equivalent using the recently proposed multiplier-less transformations namely, T1 and T2. These transformations are successful in generating circular contours even for wideband filters. Since multipliers are the most power consuming elements in a 2D filter, the multiplier-less realization calls for reduced power consumption as well as computation time. Significant reduction in the computational complexity and computation time are the highlights of our proposed design technique. Besides, the proposed discrete optimization using modified HSA can be used to solve optimization problems in other engineering disciplines, where the search space consists of integers.
文摘给出了一种适用于PHS基带系统中的高性能成形滤波器,对比两种实现方法在基带芯片中的性能,利用最少的非零比特位来表示符号数的编码技术即符号数(Canonic Sign D igit,CSD)。采用子结构共享技术改进数字滤波器结构,实现了2进制补码与CSD的转换和系统中升余弦Nyquist成形滤波器的ASIC设计,在TSMC 0.18μm工艺下进行了功能仿真、综合和后仿真。
