New Multipole Method for 3-D Capacitance Extraction

This paper describes an efficient improvement of the multipole accelerated boundary element method for 3-D capacitance extraction. The overall relations between the positions of 2-D boundary elements are considered instead of only the relations between the center-points of the elements, and a new method of cube partitioning is introduced. Numerical results are presented to demonstrate that the method is accurate and has nearly linear computational growth as O(n), where n is the number of panels/boundary elements. The proposed method is more accurate and much faster than Fastcap.

Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods

Capacitance extraction is one of the key issues in integrated circuits and also a typical electrostatic prob- lem. The dual discrete geometric method （DGM） is investigated to provide relative solutions in two-dimensional unstructured mesh space. The energy complementary characteristic and quick field energy computation thereof based on it are emphasized. Contrastive analysis between the dual finite element methods and the dual DGMs are presented both from theoretical derivation and through case studies. The DGM, taking the scalar potential as unknown on dual interlocked meshes, with simple form and good accuracy, is expected to be one of the mainstreaming methods in associated areas.

Elmore Delay Estimation of Two Adjacent Coupling Interconnects

An approach for analyzing coupling RC interconnect delay based on ＂effective capacitance＂ is presented. We compare this new method to the traditional method,which uses Miller capacitance. The results show that the new method not only improves the accuracy but also reflects the delay dependence on rise time. The method has the same complexity as the Elmore delay model and can be used in performance-driven routing optimization.

Complex fitting 3D closed-form Green's function and its application for silicon RF IC's

An approximate three-dimensional closed-form Green's function with the type of exponential function is derived over a lossy multilayered substrate by means of the Fourier transforms and a novel complex fitting approach. This Green's function is used to extract the capacitance matrix for an arbitrary three-dimensional arrangement of conductors located anywhere in the silicon IC substrate. Using this technique, the substrate loss in silicon integrated circuits can be analyzed. An example of inductor modeling is presented to show that the technique is quite effective.

Computation of sensitivities of IC interconnect parasitic capacitances to the process variation with dual discrete geometric methods

Sensitivity analysis methods help to deal with the challenges of process variation in extraction of para- sitic capacitances in an integrated circuit. The dual discrete geometric methods （DGMs）, which have been recently utilized to extract parasitic capacitances, are reviewed. The computation method based on the dual DGMs for sen- sitivities of capacitances with respect to the given process parameters is presented. As the dual DGMs utilize scalar electric potential is unknown, the capacitances are obtained effectively, and then the sensitivities are calculated conveniently.