A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator（VCO） with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between -118.5 dBc/Hz and -122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the tuning range is analyzed and derived in terms of design parameters,yielding useful equations to guide the circuit design.

A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array

A low power 9 bit 100 MS/s successive approximationregisteranalog-to-digitalconverter（SARADC） with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this capacitor array. The unit capacitor has a capacitance of 1 fF. Besides, the advanced capacitor array structure and switch mode decrease the power consumption a lot. To verify the effectiveness of this low power design, the 9 bit 100 MS/s SAR ADC is implemented in TSMC IP9M 65 nm LP CMOS technology. The measurement results demonstrate that this design achieves an effective number of bits （ENOB） of 7.4 bit, a signal-to-noise plus distortion ratio （SNDR） of 46.40 dB and a spurious-flee dynamic range （SFDR） of 62.31 dB at 100 MS/s with 1 MHz input. The SAR ADC core occupies an area of 0.030 mm2 and consumes 0.43 mW under a supply voltage of 1.2 V. The figure of merit （FOM） of the SAR ADC achieves 23.75 fJ/conv.

Design of Diode Type Un-Cooled Infrared Focal Plane Array Readout Circuit

The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.

A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Non-ideal effects of MOS capacitor in a switched capacitor waveform recorder ASIC

SCAs （Switched Capacitor Arrays） have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents （~ 4 mA max） and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 mW/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 mV with 625 kHz full-scale sine wave as input, sampling at 40 MSPS （Mega-samples per Second） and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 mV. The test results validate the feasibility of the MOS capacitor.

Design of a low power 10 bit 300 ksps multi-channel SAR ADC for wireless sensor network applications

This paper presents a low power 10 bit 300 ksps successive approximation register analog-to-digital converter （SAR ADC） which is applied in wireless sensor network （WSN） applications. A single ended energy- saving split capacitor DAC array and a latch comparator with a rail to rail input stage are utilized to implement the ADC, which can reduce power dissipation while expanding the full scale input range and improve the signal-to- noise ratio （SNR）. For power optimization the supply voltage of the SAR ADC is designed to be as low as 2 V. Four analog input channels are designed which make the ADC more suitable for WSN applications. The prototype circuit is fabricated using 3.3 V, 0.35μm 2P4M CMOS technology and occupies an active chip area of 1.23 mm2. The test results show that the power dissipation is only 200μW at a 2 V power supply and a sampling rate of 166 ksps. The calculated SNR is 58.25 dB, the ENOB is 9.38 bit and the FOM is 4.95 p J/conversion-step.

A 130 nm CMOS low-power SAR ADC for wide-band communication systems

This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.

LC voltage controlled oscillator in 0.18-μm RF CMOS

An integrated low-phase-noise voltage-controlled oscillator （VCO） has been designed and fabricated in SMIC 0.18 μm RF CMOS technology. The circuit employs an optimally designed LC resonator and a differential cross-coupling amplifier acts as a negative resistor to compensate the energy loss of the resonator. To extend the frequency tuning range, a three-bit binary-weighted switched capacitor array is used in the circuit. The testing result indicates that the VCO achieves a tuning range of 60% from 1.92 to 3.35 GHz. The phase noise of the VCO is -117.8 dBc/Hz at 1 MHz offset from the carrier frequency of 2.4 GHz. It draws 5.6 mA current from a 1.8 V supply. The VCO integrated circuit occupies a die area of 600 × 900 μm^2. It can be used in the IEEE802.1 lb based wireless local network receiver.

Wide band low phase noise QVCO based on superharmonic injection locking

A wide band, injection-coupled LC quadrature voltage control oscillator is presented. In the proposed circuit, two oscillators are injection locked by coupling their second-order harmonics in anti-phase, forcing the outputs of two oscillators into a quadrature phase state. As the common-mode point sampling the second har- monic frequency, flicker noise of the tail current is suppressed, the phase noise is reduced .The proposed design accomplishes a wide tuning frequency range by a combination of using a 5-bit switch capacitor array （SCA） for discrete tuning in addition to linearly varying AMOS varactors for continuous tuning. The proposed design has been fabricated and verified in a 0.18/zm TSMC CMOS technology process. The measurement indicates that the quadrature voltage controlled oscillator has a 41.7% tuning range from 3.53 to 5.39 GHz. The measured phase noise is 127.98 dBc/Hz at 1 MHz offset at a 1.8 V supply voltage with a power consumption of 12 mW at a carrier frequency of 4.85 GHz.

A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process

A low-phase-noise wideband ring oscillator with coarse and fine tuning techniques implemented in a standard 65 nm CMOS process is presented. Direct frequency modulation in the ring oscillator is analyzed and a switched capacitor array is introduced to produce the lower VCO gain required to suppress this effect. A two dimensional high-density stacked MOM-capacitor was adopted as the switched capacitor to make the proposed ring VCO compatible with standard CMOS processes. The designed ring VCO exhibits an output frequency from 480 to 1100 MHz, resulting in a tuning range of 78%, and the measured phase noise is -120 dBc/Hz @ 1 MHz at 495 MHz output. The VCO core consumes 3.84 mW under a 1.2 V supply voltage and the corresponding FOM is -169 dBc/Hz.