To protect superconducting qubits and enable rapid readout, optimally designed Purcell filters are essential. To suppress the off-resonant driving of untargeted readout resonators, individual Purcell filters are used ...To protect superconducting qubits and enable rapid readout, optimally designed Purcell filters are essential. To suppress the off-resonant driving of untargeted readout resonators, individual Purcell filters are used for each readout resonator.However, achieving consistent frequency between a readout resonator and a Purcell filter is a significant challenge. A systematic computational analysis is conducted to investigate how fabrication variation affects filter performance, through focusing on the coupling capacitor structure and coplanar waveguide(CPW) transmission line specifications. The results indicate that the T-type enclosing capacitor(EC), which exhibits lower structural sensitivity, is more advantageous for achieving target capacitance than the C-type EC and the interdigital capacitor(IDC). By utilizing a large-sized CPW with the T-type EC structure, fluctuations in the effective coupling strength can be reduced to 10%, given typical micro-nanofabrication variances. The numerical simulations presented in this work minimize the influence of fabrication deviations, thereby significantly improving the reliability of Purcell filter designs.展开更多
A low power 9 bit 100 MS/s successive approximationregisteranalog-to-digitalconverter（SARADC） with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this ...A low power 9 bit 100 MS/s successive approximationregisteranalog-to-digitalconverter（SARADC） with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this capacitor array. The unit capacitor has a capacitance of 1 fF. Besides, the advanced capacitor array structure and switch mode decrease the power consumption a lot. To verify the effectiveness of this low power design, the 9 bit 100 MS/s SAR ADC is implemented in TSMC IP9M 65 nm LP CMOS technology. The measurement results demonstrate that this design achieves an effective number of bits （ENOB） of 7.4 bit, a signal-to-noise plus distortion ratio （SNDR） of 46.40 dB and a spurious-flee dynamic range （SFDR） of 62.31 dB at 100 MS/s with 1 MHz input. The SAR ADC core occupies an area of 0.030 mm2 and consumes 0.43 mW under a supply voltage of 1.2 V. The figure of merit （FOM） of the SAR ADC achieves 23.75 fJ/conv.展开更多
基金Project support by the Youth Innovation Promotion Association of the Chinese Academy of Sciences (CAS) (Grant No. 2019319)the Start-up Foundation of Suzhou Institute of Nano-Tech and Nano-Bionics, CAS, Suzhou, China (Grant No. Y9AAD110)+1 种基金the Innovative and Entrepreneurial Talents Project of Jiangsu Province, China (Grant No. JSSCBS20221743)the Excellent Postdoctoral Talent Program of Jiangsu Province, China (Grant No. 2023ZB816)。
文摘To protect superconducting qubits and enable rapid readout, optimally designed Purcell filters are essential. To suppress the off-resonant driving of untargeted readout resonators, individual Purcell filters are used for each readout resonator.However, achieving consistent frequency between a readout resonator and a Purcell filter is a significant challenge. A systematic computational analysis is conducted to investigate how fabrication variation affects filter performance, through focusing on the coupling capacitor structure and coplanar waveguide(CPW) transmission line specifications. The results indicate that the T-type enclosing capacitor(EC), which exhibits lower structural sensitivity, is more advantageous for achieving target capacitance than the C-type EC and the interdigital capacitor(IDC). By utilizing a large-sized CPW with the T-type EC structure, fluctuations in the effective coupling strength can be reduced to 10%, given typical micro-nanofabrication variances. The numerical simulations presented in this work minimize the influence of fabrication deviations, thereby significantly improving the reliability of Purcell filter designs.
基金Project supported by the National High-Tech Research and Development Program of China(No.2013AA014101)
文摘A low power 9 bit 100 MS/s successive approximationregisteranalog-to-digitalconverter（SARADC） with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this capacitor array. The unit capacitor has a capacitance of 1 fF. Besides, the advanced capacitor array structure and switch mode decrease the power consumption a lot. To verify the effectiveness of this low power design, the 9 bit 100 MS/s SAR ADC is implemented in TSMC IP9M 65 nm LP CMOS technology. The measurement results demonstrate that this design achieves an effective number of bits （ENOB） of 7.4 bit, a signal-to-noise plus distortion ratio （SNDR） of 46.40 dB and a spurious-flee dynamic range （SFDR） of 62.31 dB at 100 MS/s with 1 MHz input. The SAR ADC core occupies an area of 0.030 mm2 and consumes 0.43 mW under a supply voltage of 1.2 V. The figure of merit （FOM） of the SAR ADC achieves 23.75 fJ/conv.
