Converters rely on passive filtering as a crucial element due to the high-frequency operational characteristics of power electronics.Traditional filtering methods involve a dual inductor-capacitor(LC)cell or an induct...Converters rely on passive filtering as a crucial element due to the high-frequency operational characteristics of power electronics.Traditional filtering methods involve a dual inductor-capacitor(LC)cell or an inductor-capacitor-inductor(LCL)T-circuit.However,capacitors are susceptible to wear-out mechanisms and failure modes.Nevertheless,the necessity for monitoring and regular replacement adds to an elevated cost of ownership for such systems.The utilization of an active output power filter can be used to diminish the dimensions of the LC filter and the electrolytic dc-link capacitor,even though the inclusion of capacitors remains an indispensable part of the system.This paper introduces capacitorless solid-state power filter(SSPF)for single-phase dc-ac converters.The proposed configuration is capable of generating a sinusoidal ac voltage without relying on capacitors.The proposed filter,composed of a planar transformer and an H-bridge converter operating at high frequency,injects voltage harmonics to attain a sinusoidal output voltage.The design parameters of the planar transformer are incorporated,and the impact of magnetizing and leakage inductances on the operation of the SSPF is illustrated.Theoretical analysis,supported by simulation and experimental results,are provided for a design example for a single-phase system.The total harmonic distortion observed in the output voltage is well below the IEEE 519 standard.The system operation is experimentally tested under both steady-state and dynamic conditions.A comparison with existing technology is presented,demonstrating that the proposed topology reduces the passive components used for filtering.展开更多
In electrolytic capacitorless permanent magnet synchronous motor(PMSM) drives, the DC-link voltage will fluctuate in a wide range due to the use of slim film capacitor. When the flux-weakening current is lower than-ψ...In electrolytic capacitorless permanent magnet synchronous motor(PMSM) drives, the DC-link voltage will fluctuate in a wide range due to the use of slim film capacitor. When the flux-weakening current is lower than-ψf/Ld during the high speed operation, the flux-weakening control loop will transform to a positive feedback mode, which means the reduction of flux-weakening current will lead to the acceleration of the voltage saturation, thus the whole system will be unstable. In order to solve this issue, this paper proposes a novel flux-weakening method for electrolytic capacitorless motor drives to maintain a negative feedback characteristic of the control loop during high speed operation. Based on the analysis of the instability mechanism in flux-weakening region, a quadrature voltage constrain mechanism is constructed to stabilize the system.Meanwhile, the parameters of the controller are theoretically designed for easier industrial application. The proposed algorithm is implemented on a 1.5 kW electrolytic capacitorless PMSM drive to verify the effectiveness of the flux-weakening performance.展开更多
An ultra-low power output-capacitorless low-dropout（LDO） regulator with a slew-rate-enhanced（SRE）circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and th...An ultra-low power output-capacitorless low-dropout（LDO） regulator with a slew-rate-enhanced（SRE）circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging（or discharging） the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 m A and the corresponding variation of output voltage is less than 40 m V. Moreover, the measured line regulation and load regulation are 15.38 m V/V and 0.4 m V/m A respectively.展开更多
文摘Converters rely on passive filtering as a crucial element due to the high-frequency operational characteristics of power electronics.Traditional filtering methods involve a dual inductor-capacitor(LC)cell or an inductor-capacitor-inductor(LCL)T-circuit.However,capacitors are susceptible to wear-out mechanisms and failure modes.Nevertheless,the necessity for monitoring and regular replacement adds to an elevated cost of ownership for such systems.The utilization of an active output power filter can be used to diminish the dimensions of the LC filter and the electrolytic dc-link capacitor,even though the inclusion of capacitors remains an indispensable part of the system.This paper introduces capacitorless solid-state power filter(SSPF)for single-phase dc-ac converters.The proposed configuration is capable of generating a sinusoidal ac voltage without relying on capacitors.The proposed filter,composed of a planar transformer and an H-bridge converter operating at high frequency,injects voltage harmonics to attain a sinusoidal output voltage.The design parameters of the planar transformer are incorporated,and the impact of magnetizing and leakage inductances on the operation of the SSPF is illustrated.Theoretical analysis,supported by simulation and experimental results,are provided for a design example for a single-phase system.The total harmonic distortion observed in the output voltage is well below the IEEE 519 standard.The system operation is experimentally tested under both steady-state and dynamic conditions.A comparison with existing technology is presented,demonstrating that the proposed topology reduces the passive components used for filtering.
基金supported in part by the Research Fund for the National Natural Science Foundation of China under Grant 52125701, 52007039, 51877054in part by the Key areas R&D Program of Guangdong Province China under Grant 2021B0101310001。
文摘In electrolytic capacitorless permanent magnet synchronous motor(PMSM) drives, the DC-link voltage will fluctuate in a wide range due to the use of slim film capacitor. When the flux-weakening current is lower than-ψf/Ld during the high speed operation, the flux-weakening control loop will transform to a positive feedback mode, which means the reduction of flux-weakening current will lead to the acceleration of the voltage saturation, thus the whole system will be unstable. In order to solve this issue, this paper proposes a novel flux-weakening method for electrolytic capacitorless motor drives to maintain a negative feedback characteristic of the control loop during high speed operation. Based on the analysis of the instability mechanism in flux-weakening region, a quadrature voltage constrain mechanism is constructed to stabilize the system.Meanwhile, the parameters of the controller are theoretically designed for easier industrial application. The proposed algorithm is implemented on a 1.5 kW electrolytic capacitorless PMSM drive to verify the effectiveness of the flux-weakening performance.
基金Project supported by the National Natural Science Foundation of China(Nos.61401137,61404043,61674049)
文摘An ultra-low power output-capacitorless low-dropout（LDO） regulator with a slew-rate-enhanced（SRE）circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging（or discharging） the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 m A and the corresponding variation of output voltage is less than 40 m V. Moreover, the measured line regulation and load regulation are 15.38 m V/V and 0.4 m V/m A respectively.
