In electrolytic capacitorless permanent magnet synchronous motor(PMSM) drives, the DC-link voltage will fluctuate in a wide range due to the use of slim film capacitor. When the flux-weakening current is lower than-ψ...In electrolytic capacitorless permanent magnet synchronous motor(PMSM) drives, the DC-link voltage will fluctuate in a wide range due to the use of slim film capacitor. When the flux-weakening current is lower than-ψf/Ld during the high speed operation, the flux-weakening control loop will transform to a positive feedback mode, which means the reduction of flux-weakening current will lead to the acceleration of the voltage saturation, thus the whole system will be unstable. In order to solve this issue, this paper proposes a novel flux-weakening method for electrolytic capacitorless motor drives to maintain a negative feedback characteristic of the control loop during high speed operation. Based on the analysis of the instability mechanism in flux-weakening region, a quadrature voltage constrain mechanism is constructed to stabilize the system.Meanwhile, the parameters of the controller are theoretically designed for easier industrial application. The proposed algorithm is implemented on a 1.5 kW electrolytic capacitorless PMSM drive to verify the effectiveness of the flux-weakening performance.展开更多
An ultra-low power output-capacitorless low-dropout（LDO） regulator with a slew-rate-enhanced（SRE）circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and th...An ultra-low power output-capacitorless low-dropout（LDO） regulator with a slew-rate-enhanced（SRE）circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging（or discharging） the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 m A and the corresponding variation of output voltage is less than 40 m V. Moreover, the measured line regulation and load regulation are 15.38 m V/V and 0.4 m V/m A respectively.展开更多
基金supported in part by the Research Fund for the National Natural Science Foundation of China under Grant 52125701, 52007039, 51877054in part by the Key areas R&D Program of Guangdong Province China under Grant 2021B0101310001。
文摘In electrolytic capacitorless permanent magnet synchronous motor(PMSM) drives, the DC-link voltage will fluctuate in a wide range due to the use of slim film capacitor. When the flux-weakening current is lower than-ψf/Ld during the high speed operation, the flux-weakening control loop will transform to a positive feedback mode, which means the reduction of flux-weakening current will lead to the acceleration of the voltage saturation, thus the whole system will be unstable. In order to solve this issue, this paper proposes a novel flux-weakening method for electrolytic capacitorless motor drives to maintain a negative feedback characteristic of the control loop during high speed operation. Based on the analysis of the instability mechanism in flux-weakening region, a quadrature voltage constrain mechanism is constructed to stabilize the system.Meanwhile, the parameters of the controller are theoretically designed for easier industrial application. The proposed algorithm is implemented on a 1.5 kW electrolytic capacitorless PMSM drive to verify the effectiveness of the flux-weakening performance.
基金Project supported by the National Natural Science Foundation of China(Nos.61401137,61404043,61674049)
文摘An ultra-low power output-capacitorless low-dropout（LDO） regulator with a slew-rate-enhanced（SRE）circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging（or discharging） the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 m A and the corresponding variation of output voltage is less than 40 m V. Moreover, the measured line regulation and load regulation are 15.38 m V/V and 0.4 m V/m A respectively.
