A monolithic low-power and low-phase-noise digitally controlled oscillator （DCO） based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18 μm CMOS process with six meta...A monolithic low-power and low-phase-noise digitally controlled oscillator （DCO） based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18 μm CMOS process with six metal layers. A third new way to change capacitance is proposed and implemented in this work. Results show that the phase noise at I MHz offset frequency is below -122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also, the DCO can work at low supply voltage conditions with a 1.6 V power supply and 4.1 mA supply current for the DCO＇s core circuit, achieving a phase-noise of-121.5 dBc/Hz at offset of 1 MHz. It demonstrates that the supply pushing of DCO is less than 10 MHz/V.展开更多
A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage change...A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.展开更多
以我国自主创新的CAPS(China area positioning system)导航定位系统为研究平台,提出了CAPS卫星信号模拟器的系统架构,给出了总体设计框图,对各模块的功能进行了划分和设计。针对CAPS导航系统的特点,开展了模拟器关键技术的研究,给出了...以我国自主创新的CAPS(China area positioning system)导航定位系统为研究平台,提出了CAPS卫星信号模拟器的系统架构,给出了总体设计框图,对各模块的功能进行了划分和设计。针对CAPS导航系统的特点,开展了模拟器关键技术的研究,给出了相关参数的计算方法。利用已开发出的成型的CAPS模拟器进行测试,结果表明:本文的设计方法是可行的,该模拟器可以用于测试接收机的捕获、跟踪和定位性能等。展开更多
文摘A monolithic low-power and low-phase-noise digitally controlled oscillator （DCO） based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18 μm CMOS process with six metal layers. A third new way to change capacitance is proposed and implemented in this work. Results show that the phase noise at I MHz offset frequency is below -122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also, the DCO can work at low supply voltage conditions with a 1.6 V power supply and 4.1 mA supply current for the DCO＇s core circuit, achieving a phase-noise of-121.5 dBc/Hz at offset of 1 MHz. It demonstrates that the supply pushing of DCO is less than 10 MHz/V.
文摘A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.
文摘以我国自主创新的CAPS(China area positioning system)导航定位系统为研究平台,提出了CAPS卫星信号模拟器的系统架构,给出了总体设计框图,对各模块的功能进行了划分和设计。针对CAPS导航系统的特点,开展了模拟器关键技术的研究,给出了相关参数的计算方法。利用已开发出的成型的CAPS模拟器进行测试,结果表明:本文的设计方法是可行的,该模拟器可以用于测试接收机的捕获、跟踪和定位性能等。
