A novel frequency compensation technique for three-stage amplifier with dual complex pole-zero (DCP) cancellation is proposed. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in featur...A novel frequency compensation technique for three-stage amplifier with dual complex pole-zero (DCP) cancellation is proposed. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in feature that frequency response of the three-stage amplifier exhibits that of a single-pole system. Thus the gain-bandwidth (GBW) is expected to be increased several times compared to the conventional nested miller compensation (NMC) approach. Moreover, this technique requires only one very small compensation capacitor even when driving a big load capacitor. A GBW 4.63 MHz, DC gain 100 dB, PM 90o and power dissipation 0.87 mW can be achieved for a load capacitor 100 pF with a single Miller compensation capacitor 2 pF at a ±1V supply in a standard 0.6-μm CMOS technology.展开更多
以设计输出电流为800mA的高稳定线性稳压器(low-dropout voltage regulator,LDO)为目标,利用工作在线性区的MOS管具有压控电阻特性,构造零点跟踪电路以抵消随输出电流变化的极点,并且采用了改进型米勒补偿方案使电路系统具有60°的...以设计输出电流为800mA的高稳定线性稳压器(low-dropout voltage regulator,LDO)为目标,利用工作在线性区的MOS管具有压控电阻特性,构造零点跟踪电路以抵消随输出电流变化的极点,并且采用了改进型米勒补偿方案使电路系统具有60°的相位裕度,达到了大输出电流下的高稳定性要求.另外,分析了电路在转换发生时电路结构参数和负载整流特性的关系,提出了一种能在瞬间提供大电流的转换速率加强电路,达到了在负载电流从800mA到10mA跳变时,输出电压的跳变量控制在60mV以内,并且最长输出电压恢复时间在500μs以内.芯片采用CSMC公司的0.6μm CMOS数模混合信号工艺设计,并经过流片和测试,测试结果验证了设计方案.展开更多
提出了一种片上集成的低功耗无电容型LDO（low drop out）电路。该电路采用折叠型eascode运放作为误差放大器，通过消除零点的密勒补偿技术提高了环路稳定性；并在电路中加入了一种新的限流保护结构以保证输出电流过大时对LDO的输出进...提出了一种片上集成的低功耗无电容型LDO（low drop out）电路。该电路采用折叠型eascode运放作为误差放大器，通过消除零点的密勒补偿技术提高了环路稳定性；并在电路中加入了一种新的限流保护结构以保证输出电流过大时对LDO的输出进行保护。此外，在电路中加入了省电模式，可在保持LDO输出1．8V情况下节省大于70％的功耗。该设计采用HHNEC0．13μmCMOS工艺，仿真结果显示：在2．5～5．5V电源供电、各个工艺角及温度变化条件下，LDO输出的线性调整率小于2．3mV／V，负载调整率小于14μV／mA，温度系数小于27×10^-6／℃；在正常工作模式下，整个LDO消耗85μA电流；在省电模式下仅消耗23斗A电流。展开更多
文摘A novel frequency compensation technique for three-stage amplifier with dual complex pole-zero (DCP) cancellation is proposed. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in feature that frequency response of the three-stage amplifier exhibits that of a single-pole system. Thus the gain-bandwidth (GBW) is expected to be increased several times compared to the conventional nested miller compensation (NMC) approach. Moreover, this technique requires only one very small compensation capacitor even when driving a big load capacitor. A GBW 4.63 MHz, DC gain 100 dB, PM 90o and power dissipation 0.87 mW can be achieved for a load capacitor 100 pF with a single Miller compensation capacitor 2 pF at a ±1V supply in a standard 0.6-μm CMOS technology.
文摘以设计输出电流为800mA的高稳定线性稳压器(low-dropout voltage regulator,LDO)为目标,利用工作在线性区的MOS管具有压控电阻特性,构造零点跟踪电路以抵消随输出电流变化的极点,并且采用了改进型米勒补偿方案使电路系统具有60°的相位裕度,达到了大输出电流下的高稳定性要求.另外,分析了电路在转换发生时电路结构参数和负载整流特性的关系,提出了一种能在瞬间提供大电流的转换速率加强电路,达到了在负载电流从800mA到10mA跳变时,输出电压的跳变量控制在60mV以内,并且最长输出电压恢复时间在500μs以内.芯片采用CSMC公司的0.6μm CMOS数模混合信号工艺设计,并经过流片和测试,测试结果验证了设计方案.
文摘提出了一种片上集成的低功耗无电容型LDO（low drop out）电路。该电路采用折叠型eascode运放作为误差放大器，通过消除零点的密勒补偿技术提高了环路稳定性；并在电路中加入了一种新的限流保护结构以保证输出电流过大时对LDO的输出进行保护。此外，在电路中加入了省电模式，可在保持LDO输出1．8V情况下节省大于70％的功耗。该设计采用HHNEC0．13μmCMOS工艺，仿真结果显示：在2．5～5．5V电源供电、各个工艺角及温度变化条件下，LDO输出的线性调整率小于2．3mV／V，负载调整率小于14μV／mA，温度系数小于27×10^-6／℃；在正常工作模式下，整个LDO消耗85μA电流；在省电模式下仅消耗23斗A电流。
