Influence of channel length on discharge performance of anode layer Hall thruster studied by particle-in-cell simulation

Hall thruster has the advantages of simple structure, high specific impulse, high efficiency, and long service life, and so on. It is suitable for spacecraft attitude control, North and South position keeping, and other track tasks. The anode layer Hall thruster is a kind of Hall thruster. The thruster has a longer anode area and a relatively short discharge channel. In this paper, the effect of the channel length on the performance of the anode layer Hall thruster is simulated by the PIC simulation method. The simulation results show that the change of the channel length has significant effect on the plasma parameters, such as potential and plasma density and so on. The ionization region mainly concentrates at the hollow anode outlet position, and can gradually move toward the channel outlet as the channel length decreases. The collision between the ions and the wall increases with the channel length increasing. So the proper shortening of the channel length can increase the life of the thruster. Besides, the results show that there is a best choice of the channel length for obtaining the best performance. In this paper, thruster has the best performance under a channel length of 5 mm.

Impact of Channel Length and Width for Charge Transportation of Graphene Field Effect Transistor

The effect of channel length and width on the large and small-signal parameters of the graphene field effect transistor have been explored using an analytical approach.In the case of faster saturation as well as extremely high transit frequency,the graphene field effect transistor shows outstanding performance.From the transfer curve,it is observed that there is a positive shift of Dirac point from the voltage of 0.15 V to 0.35 V because of reducing channel length from 440 nm to 20 nm and this curve depicts that graphene shows ambipolar behavior.Besides,it is found that because of widening channel the drain current increases and the maximum current is found approximately 2.4 mA and 6 mA for channel width 2μm and 5μm respectively.Furthermore,an approximate symmetrical capacitance-voltage(C-V)characteristic of the graphene field effect transistor is obtained and the capacitance reduces when the channel length decreases but the capacitance can be increased by raising the channel width.In addition,a high transconductance,that demands high-speed radio frequency(RF)applications,of 6.4 mS at channel length 20 nm and 4.45 mS at channel width 5μm along with a high transit frequency of 3.95 THz have been found that demands high-speed radio frequency applications.

Dependence of short channel length on negative/positive bias temperature instability (NBTI/PBTI) for 3D FinFET devices

A comprehensive study of the negative and positive bias temperature instability(NBTI/PBTI)of 3D FinFET devices with different small channel lengths is presented.It is found while with the channel lengths shrinking from 100 nm to 30 nm,both the NBTI characteristics of p-FinFET and PBTI characteristics of n-FinFET turn better.Moreover,the channel length dependence on NBTI is more serious than that on PBTI.Through the analysis of the physical mechanism of BTI and the simulation of 3-D stress in the FinFET device,a physical mechanism of the channel length dependence on NBTI/PBTI is proposed.Both extra fluorine passivation in the corner of bulk oxide and stronger channel stress in p-FinFETs with shorter channel length causes less NBTI issue,while the extra nitrogen passivation in the corner of bulk oxide induces less PBTI degradation as the channel length decreasing for n-FinFETs.The mechanism well matches the experimental result and provides one helpful guide for the improvement of reliability issues in the advanced FinFET process.

Shot Noise Suppression in a Quantum Point Contact with Short Channel Length

An experimental study on the current shot noise of a quantum point contact with short channel length is reported. The experimentally measured maximum energy level spacing between the ground and the first excited state of the device reached up to 7.5meV, probably due to the hard wall confinement by using shallow electron gas and sharp point contact geometry. The two-dimensionM non-equilibrium shot noise contour map shows noise suppression characteristics in a wide range of bias voltage. Fano factor analysis indicates spin-polarized transport through a short quantum point contact.

Effective Channel Length Degradation under Hot-Carrier Stressing

This article describes the effective channel length degradation under hot carrier stressing. The extraction is based on the IDs-Vcs characteristics by maximum transconductance （maximum slope of IDs ＆ VGS） in the linear region. The transconductance characteristics are determine for the several devices of difference drawn channel length. The effective channel length of submicron LDD （Lightly Doped Drain） NMOSFETs （Metal Oxide Semiconductor Field Effect Transistor） under hot carrier stressing was measured at the stress time varying from zero to 10,000 seconds. It is shown that the effective channel length was increased with time. This is caused by charges trapping in the oxide during stress. The increased of effective channel length （△Leff） is seem to be increased sharply as the gate channel length is decrease.

Anomalous Channel Length Dependence of Hot-Carrier-Induced Saturation Drain Current Degradation in n-Type MOSFETs

The dependencies of hot-carrier-induced degradations on the effective channel length Lch,eff are investigated for n-type metal-oxide-semiconductor field effect transistor （MOSFETs）. Our experiments find that, with decreasing Lch,eff, the saturation drain current （Iasat ） degradation is unexpectedly alleviated. The further study demonstrates that the anomalous Lch,eff dependence of Idsat degradation is induced by the increasing influence of the substrate current degradation on the lazar degradation with Lch,eff reducing.

Perpendicular intergrowth ZSM-5 plates with shortened 10-MR pores

ZSM-5 plates with a perpendicular intergrowth structure was synthesized by using a simple amine as the structure directing agent under hydrothermal conditions,in which the mother plate and the perpendicularly standing plates oriented along the(010)and(100)planes of MFI crystals,respectively.During the crystallization process,the mother plate was initially formed on the surface of the amorphous solid gel,while a set of parallel plates perpendicularly grew on its surface,via a homogeneous nucleation mechanism.The mother plate and the perpendicular plates had a similar thickness of 100-200 nm and were characterized by considerably shortened straight and zigzag 10 member ring pores,respectively.This unique intergrowth structure greatly facilitated the diffusion of the reactive molecules in HZSM-5 crystals during methanol conversion to hydrocarbons.

Influence of epitaxial layer structure and cell structure on electrical performance of 6.5 kV SiC MOSFET

Silicon carbide(SiC)material features a wide bandgap and high critical breakdown field intensity.It also plays an important role in the high efficiency and miniaturization of power electronic equipment.It is an ideal choice for new power electronic devices,especially in smart grids and high-speed trains.In the medium and high voltage fields,SiC devices with a blocking voltage of more than 6.5 kV will have a wide range of applications.In this paper,we study the influence of epitaxial material properties on the static characteristics of 6.5 kV SiC MOSFET.6.5 kV SiC MOSFETs with different channel lengths and JFET region widths are manufactured on three wafers and analyzed.The FN tunneling of gate oxide,HTGB and HTRB tests are performed and provide data support for the industrialization process for medium/high voltage SiC MOSFETs.

Analysis on the positive dependence of channel length on ESD failure current of a GGNMOS in a 5 V CMOS

Contrary to general understanding, a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process. Such a phenomenon in a gate-grounded NMOSFET （GGNMOS） was investigated, and the current spreading effect was verified as the predominant factor. Due to transmission line pulse （TLP） measurements and Sentaurus technology computer aided design （TCAD） 2-D numerical simulations, parameters such as current gain, on-resistance and power density were discussed in detail.

Comparative study of leakage power in CNTFET over MOSFET device

A comparison of the CNTFET device with the MOSFET device in the nanometer regime is reported. The characteristics of both devices are observed as varying the oxide thickness. Thereafter, we have analyzed the effect of the chiral vector and the temperature on the threshold voltage of the CNTFET device. After simulation on the HSPICE tool, we observed that the high threshold voltage can be achieved at a low chiral vector pair. It is also observed that the effect of temperature on the threshold voltage of the CNTFET is negligibly small. After that, we have analyzed the channel length variation and their impact on the threshold voltage of the CNTFET as well as MOSFET devices. We found an anomalous effect from our simulation result that the threshold voltage increases with decreasing the channel length in CNTFET devices; this is contrary to the well known short channel effect. It is observed that at below the 10 nm channel length, the threshold voltage is increased rapidly in the case of the CNTFET device, whereas in the case of the MOSFET device, the threshold voltage decreases drastically.

From parabolic approximation to evanescent mode analysis on SOI MOSFET

Subthreshold conduction is governed by the potential distribution. We focus on full two-dimensional（2D） analytical modeling in order to evaluate the 2D potential profile within the active area of Fin FET structure.Surfaces and interfaces, which are key nanowire elements, are carefully studied. Different structures have different boundary conditions, and therefore different effects on the potential distributions. A range of models in Fin FET are reviewed in this paper. Parabolic approximation and evanescent mode are two different basic math methods to simplify the Poisson＇s equation. Both superposition method and parabolic approximation are widely used in heavily doped devices. It is helpful to learn performances of MOSFETs with different structures. These two methods achieved improvement to face different structures from heavily doped devices or lightly doped devices to junctionless transistors.