Design of a CMOS Adaptive Charge Pump with Dynamic Current Matching

A novel structure for a charge pump circuit is proposed, in which the charge-pump （CP） current can adaptively regulated according to phase-locked loops （PLL） frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor （CMOS） mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.

Self-Balanced Charge Pump with Fast Lock Circuit

A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.

A PLL Clock Frequency Multiplier Using Dynamic Current Matching Adaptive Charge-Pump and VCO Frequency Reuse

A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .

Design and noise analysis of a fully-differential charge pump for phase-locked loops

A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.

Short locking time and low jitter phase-locked loop based on slope charge pump control

A novel structure of a phase-locked loop （PLL） characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector （PFD） to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.

应用于TDC电路的低相噪电荷泵锁相环

基于SMIC 0.18μm CMOS工艺实现了一种低相位噪声的四级差分延迟振荡器结构锁相环。通过增加额外的充、放电支路和单位增益放大器优化电荷泵结构,有效减少锁相环电路中的时钟馈通、电荷共享等非理想因素,同时采用重定时结构的反馈回路消除了电路中噪声的积累。测试结果表明,当输入参考频率为40 MHz时,锁相环的输出中心频率在5μs内稳定到960 MHz,相位噪声为-125 dBc/Hz@1 MHz,较好解决了传统锁相环结构由于噪声抑制性能差而无法满足高精度时间-数字转换(Time-to-digital conversion,TDC)电路要求的问题。

低抖动电荷泵锁相环设计及其Simulink建模仿真

随着集成电路工艺技术的进步,电路工作频率越来越高,对时钟信号的抖动和相噪也提出了更高的要求。针对锁相环电路参数多、结构复杂、瞬态仿真耗时长等问题,通过建立电荷泵锁相环系统环路数学模型,并运用MATLAB/Simulink对其进行负反馈系统建模,实现对电荷泵锁相环的快速动态仿真。在TSMC 65 nm CMOS工艺节点下,完成了锁相环的电路设计、版图绘制、物理验证并提取寄生参数及后仿真,得到一款典型值:输入频率为30 MHz,锁定频率1.5 GHz的低抖动电荷泵锁相环。后仿真结果表明该PLL电路性能指标良好,在典型值条件下,PLL的锁定时间为10μs,锁定时峰峰值抖动为2.68 ps,时钟信号占空比为45%。

适用于宽带宽的快速锁定电荷泵锁相环设计

文章基于TSMC 0.18μm CMOS工艺,设计一种适用于宽带宽下可快速锁定的电荷泵锁相环(charge pump phase-locked loop,CPPLL)。采用一种自适应快速锁定结构,比较参考信号与反馈信号的频率、相位,通过开启大电流与小电流快速锁定通路,对环路滤波器中的电容进行放电使得压控振荡器的控制电压降至锁定电平附近的方法,最大限度地减小锁定时间。通过SPECTRE仿真验证表明,在1.8 V供电电压下,输出频率为768 MHz时,锁定时间仅需1.5μs,缩短了78%,功耗为3.6 mW。

一种基于22 nm FDSOI工艺的低噪声快速锁定电荷泵锁相环

基于22 nm全耗尽绝缘体上硅(Fully Depleted Silicon-On-Insulator,FDSOI)工艺设计了一种能够快速锁定的电荷泵锁相环(Charge Pump Phase Locked Loop,CPPLL)电路,该锁相环利用FDSOI器件背栅偏置的特点来提升压控振荡器性能,采用了无死区的鉴频鉴相器(Phase Frequency Detector,PFD)和低失配电流电荷泵(Charge Pump,CP)以及低相位噪声结构的压控振荡器(Voltage Controlled Oscillator,VCO)。研究了相位噪声的理论模型,基于理论参数进行电路设计和电路噪声降低。仿真结果表明,该锁相环锁定时间3μs,CP电流失配小于1%,VCO相噪水平达到-100.4 dBc/Hz@1 MHz,版图面积为0.14 mm^(2)。该锁相环具有锁定速度快,相噪低,频率精准等优点。

一种应用于DDR的低抖动锁相环设计

针对双倍速率同步动态随机存储器中锁相环抖动性能较差的问题,基于55nmCMOS工艺设计了一种低抖动锁相环。采用负反馈型比例-积分结构控制的电荷泵来获得良好的抖动性能并实现快速锁定,环型振荡器采用伪差分结构的预充电方式来提升时钟翻转速度。后仿真结果显示,在2.5V电源供电条件下,锁相环能够在2μs内锁定在3.2GHz频率处,其相位噪声约为-96.2dBc/Hz@1MHz。芯片测试结果显示,输出时钟周期抖动为-27.7~23.2ps。

基于55 nm CMOS工艺的小数分频电荷泵锁相环设计

为解决无线射频收发机中锁相环存在的功耗高、精度低、不能小数分频等问题,提出了一种基于55 nmCMOS工艺的小数分频电荷泵锁相环,降低噪声对电路性能的影响,为无线收发机提供稳定的震荡信号。采用三阶噪声整形结构的数字Σ-Δ调制器,设计了24位高精度可编程小数分频器。同时设计了一种线性移位寄存器,产生随机数列降低小数杂散。采用单位增益缓冲器有效地降低了电荷泵的电流失配。SPECTRE仿真结果表明,电荷泵的充放电流失配为0.87%,锁相环的输出频率范围为2.1~2.9 GHz,相位噪声为-108 dBc/Hz@1 MHz,分频比为5~128,锁定时间小于3.5μs,功耗为8.56 mW。

一种高性能宽范围锁相环的设计与实现

采用CMOS工艺技术,设计了一款基于双环路滤波器的高性能、宽范围锁相环。该锁相环电路包括可调延迟的鉴频鉴相器、电荷泵、双环路有源滤波器、多频带的压控振荡器和可编程分频器模块。与无源滤波器结构相比,双环滤波的结构将滤波电容面积减小3/4,该锁相环整体版图面积为405μm×480μm,经过仿真测试,锁相环能够提供的输出频率范围为140MHz~1.5GHz,整体功耗为6.85mW。设计的锁相环其流片测试结果显示:当输出频率为1.5GHz时,均方根抖动为8.92ps;当中心频率为820MHz时,均方根抖动为6.01ps,测试结果表明设计的这款锁相环输出频率能够满足使用需求。

Stability Analysis of CPLL with Loop Delay

In this paper,a discrete-time analysis of the third-order charge-pump based phase-locked loops (CPLLs) is presented in the presence of loop delay.The z-domain analysis of the closed-loop transfer function is derived and compared with the traditional s-domain method.The simulation results under SPECTRE show that,due to the sampling nature of CPLL,the traditional s-domain analysis is unable to predict its jitter peaking accurately,especially when the loop delay is taken into consideration.The impact of loop delay on the stability of the third-order CPLL system is further analyzed based on the proposed way.The stability limit of the wide bandwidth CPLL with loop delay is calculated.The circuit simulation results agree well with mathematical analysis.

一种电流失配自适应补偿宽带锁相环设计

针对宽带自偏置锁相环(PLL)中存在严重的电荷泵电流失配问题,提出了一种电流失配自适应补偿自偏置锁相环。锁相环通过放大并提取参考时钟与反馈时钟的锁定相位误差脉冲,利用误差脉冲作为误差判决电路的控制时钟,通过逐次逼近方法自适应控制补偿电流的大小,逐渐减小鉴相误差,从而减小了锁相环输出时钟信号抖动。锁相环基于40 nm CMOS工艺进行设计,后仿真结果表明,当输出时钟频率为5 GHz时,电荷泵输出噪声从-115.7 dBc/Hz@1 MHz降低至-117.7 dBc/Hz@1 MHz,均方根抖动从4.6 ps降低至1.6 ps,峰峰值抖动从10.3 ps降低至4.7 ps。锁相环输出时钟频率为2~5 GHz时,补偿电路具有良好的补偿效果。

一种应用于HDMI接收端的宽频带锁相环设计

基于110 nm CMOS工艺设计了一种应用于HDMI接收端电路的宽频带低抖动锁相环。采用一种改进型双环结构电荷泵,在25~250 MHz的宽输入频率范围内实现了快速锁定。通过高相噪性能的伪差分环形振荡器产生了调谐范围为125 MHz~1.25 GHz的时钟信号。仿真实验结果表明,该锁相环的锁定时间小于1.2μs,在振荡器工作频率为0.8 GHz时,其相位噪声为-100.0 dBc/Hz@1 MHz,输出时钟峰峰值抖动为4.49 ps。

一种基于三管开关结构的改进型电荷泵设计

提出了一种改进型电荷泵,通过三管开关结构减小了时钟馈通效应,同时将电流舵结构与全差分电荷泵结构相结合,在提升开关速度的同时,抑制了电流失配、电荷共享和电荷注入等非理想效应。仿真实验结果表明,在电荷泵的充放电电流为10μA时,时钟馈通所引起的尖峰电流最大值仅为11.26μA,所产生的压控振荡器控制电压纹波降至50%。将其应用于锁相环系统,锁相环输出时钟抖动从118 ps降低到36 ps。

一种自适应可重构宽带低抖动锁相环时钟

为满足不同速率的串行收发数据采样需求,基于可重构电荷泵阵列设计了一种低抖动宽带锁相环时钟。根据锁相环倍频系数,自适应匹配电荷泵阵列输出电流,实现了较宽频率变换的低抖动输出时钟。锁相环时钟采用40 nm CMOS工艺设计,面积为367.227*569.344μm^(2)。测试结果表明,锁相环调谐范围为1~4 GHz,输出时钟均方根抖动为3.01 ps@1.25 GHz和3.98 ps@4 GHz,峰峰值抖动小于0.1UI。

一种低噪声全差分电荷泵型锁相环的实现

采用HHGrace 180 nm CMOS工艺实现了一款低噪声全差分电荷泵型锁相环,可为物理层芯片提供精确且稳定的时钟信号。鉴频鉴相器和分频器采用电流模逻辑电路构成基本单元,提高了锁相环的工作速度;设计了一种改进型差分电荷泵,引入共模反馈使电荷泵输出电压的静态工作点更加稳定,提高了锁相环的相位噪声性能。测试结果表明,该锁相环功耗小于24 mW,芯片面积为510μm×620μm,锁定时间小于2.5μs,相位噪声为-108 dBc/Hz@100 kHz、-113 dBc/Hz@1 MHz。

A radiation-hardened-by-design technique for improving single-event transient tolerance of charge pumps in PLLs

A radiation-hardened-by-design （RHBD） technique for phase-locked loops （PLLs） has been developed for single-event transient （SET） mitigation. By presenting a novel SET-resistant complementary current limiter （CCL） and implementing it between the charge pump （CP） and the loop filter （LPF）, the PLL＇s single-event susceptibility is significantly decreased in the presence of SETs in CPs, whereas it has little impact on the loop parameters in the absence of SETs in CPs. Transistor-level simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator （VCO） by up to 93.1% and reduce the recovery time of the PLL by up to 79.0%. Moreover, the CCL circuit can also accelerate the PLL recovery procedure from loss of lock due to phase or frequency shift, as well as a single-event strike.