Column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor

High linearity and low noise column readout chain are two key factors in CMOS image sensor.However,offset mismatch and charge sharing always exist in the conventional column wise readout implementation,even adopting the technology of correlated double sample.A simple column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor is proposed in this paper.Based on the bottom plate sampling and fixed common level method,this novel design can avoid the offset nonuniformity between the two buffers.Also,the single buffer and switched capacitor technique can effectively suppress the charge sharing caused by the varied operating point.The proposed approach is experimentally verified in a 1024×1024 prototype chip designed and fabricated in 55 nm low power CMOS process.The measurement results show that the linear range is extended by 20%,the readout noise of bright and dark fields is reduced by 40%and 30%respectively,and the improved photo response nonuniformity is up to 1.16%.Finally,a raw sample image taken by the prototype sensor shows the excellent practical performance.

The dual role of multiple-transistor charge sharing collection in single-event transients

As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients （SETs） due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal–oxide semiconductor field-effect transistor （PMOS FET）, but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies.

Temperature dependence of the P-hit single event transient pulse width in a three-transistor inverter chain

A comparison of the temperature dependence of the P-hit single event transient （SET） in a two-transistor （2T） inverter with that in a three-transistor （3T） inverter is carried out based on a three-dimensional numerical simulation. Due to the significantly distinct mechanisms of the single event change collection in the 2T and the 3T inverters, the temperature plays different roles in the SET production and propagation. The SET pulse will be significantly broadened in the 2T inverter chain while will be compressed in the 3T inverter chain as temperature increases. The investigation provides a new insight into the SET mitigation under the extreme environment, where both the high temperature and the single event effects should be considered. The 3T inverter layout structure （or similar layout structures） will be a better solution for spaceborne integrated circuit design for extreme environments.

Effect of supply voltage and body-biasing on single-event transient pulse quenching in bulk fin field-effect-transistor process

Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor （FinFET） technology. However, the studies of charge sharing induced single-event transient （SET） pulse quenching with bulk FinFET are reported seldomly. Using three-dimensional technology computer aided design （3DTCAD） mixed-mode simulations, the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk FinFET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing （RBB）, the circuit with forward body-biasing （FBB） is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least. This can provide guidance for radiation-hardened bulk FinFET technology especially in low power and high performance applications.

Temperature dependence of charge sharing and MBU sensitivity induced by a heavy ion

The temperature dependence of charge sharing in a 130 nm CMOS technology has been investigated over a temperature range of 200 to 420 K.Device simulation results show that the charge sharing collection increases by 66%-325% when the temperature rises.The LETth of a MBU in two SRAM cells and one DICE cell is also quantified.Besides charge sharing, the circuit response＇s temperature dependence also has a significant influence on the LETth.

Development of large-area quadrant silicon detector for charged particles

The quadrant silicon detector, a kind of passivated implanted planar silicon detector with quadrant structure on the junction side, gained its wide application in charged particle detection. In this paper, the manufacturing procedure, performance test and results of the quadrant silicon detector developed recently at the China Institute of Atomic Energy are presented. The detector is about 300 μm thick with a 48 mm×48 mm active area.The leakage current under the full depletion bias voltage of-16 V is about 2.5 n A, and the rise time is better than160 ns. The energy resolution for a 5.157 Me V α-particle is around the level of 1%. Charge sharing effects between the neighboring quads, leading to complicated correlations between two quads, were observed when α particles illuminated on the junction side. It is explained as a result of distortion of the electric field of the inter-quad region.Such an event is only about 0.6% of all events and can be neglected in an actual application.

A trusted architecture for EV shared charging based on blockchain technology

With the development of the Energy Internet and the support of the subsidy policies of various countries,Electric Vehicles(EVs)have ushered in a golden development period.However,the development of EVs needs to solve the problems of insufficient charging piles(CPs)and difficulty in finding CPs.In order to solve the problem of difficult charging of EVs,the concept of shared charging came into being,in which idle CPs or private CPs are shared to meet the charging needs of more people and improve the utilization rate of CPs.However,the shared charging scheme implemented by third-party platforms faces the issue of trust lacking.This paper proposes a blockchain architecture for shared charging,which can use the blockchain to build a trust environment involving private pile owners,charging pile(CP)operators,Electric Vehicle(EV)users,etc..The blockchain architecture also contains the block structure where pointer was added for quick search,contract content that can automatically execute multi-party contracts to achieve secure computing and reputation-based incentive mechanism to provide high-quality charging services in detail.This architecture establishes the multi-party trust environment for shared charging from three aspects:secure storage,secure computing,and secure incentives.

Effect of charge sharing on the single event transient response of CMOS logic gates

This paper presents three new types of pulse quenching mechanism（NMOS-to-PMOS,PMOS-to-NMOS and NMOS-to-NMOS） and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node. The three major contributions of this paper are：（1） with the exception of PMOS-to-PMOS,pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process.（2） Pulse quenching in general correlates weakly with ion LET,but strongly with incident angle and layout style（i.e.spacing between transistors and n-well contact area）.（3） Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.

Charge sharing effect on 600 μm pitch pixelated CZT detector for imaging applications

We are currently investigating the spatial resolution of highly pixelated Cadmium Zinc Telluride （CZT） detector for imaging application. A 20 mm × 20 mm× 5 mm CZT substrate was fabricated with 600 μm pitch pixels （500μm anode pixels with 100 μm gap） and coplanar cathode. Charge sharing between two pixels was studied using collimated a 122 keV gamma ray source. Experiments show a resolution of 125 μm FWHM for double-pixel charge sharing events when the 600 μm pixelated and 5 mm thick CZT detector biased at -1000 V. In addition, we analyzed the energy response of the 600 μm pitch pixelated CZT detector.

Research on single event transient pulse quenching effect in 90 nm CMOS technology

Since single event transient pulse quenching can reduce the SET(single event transient) pulsewidths effectively,the charge collected by passive device should be maximized in order to minimize the propagated SET.From the perspective of the layout and circuit design,the SET pulsewidths can be greatly inhibited by minimizing the layout spacing and signal propagation delay,which sheds new light on the radiation-hardened ICs(integrated circuits) design.Studies show that the SET pulsewidths of propagation are not in direct proportion to the LET(linear energy transfer) of incident particles,thus the defining of the LET threshold should be noted when SET/SEU(single event upset) occurs for the radiation-hardened design.The capability of anti-radiation meets the demand when LET is high but some soft errors may occur when LET is low.Therefore,radiation experiments should be focused on evaluating the LET that demonstrates the worst response to the circuit.

Analysis of process variations impact on the single-event transient quenching in 65 nm CMOS combinational circuits

Single-event transient pulse quenching （Quenching effect） is employed to effectively mitigate WSET （SET pulse width）. It en- hanced along with the increased charge sharing which is norm for future advanced technologies. As technology scales, param- eter variation is another serious issue that significantly affects circuit＇s performance and single-event response. Monte Carlo simulations combined with TCAD （Technology Computer-Aided Design） simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching. Studies show that charge sharing induce a wider WSET spread range. The difference of WSET range between no quenching and quenching is smaller in NMOS （N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor） simulation than that in PMOS＇ （P-Channel Met- N-Oxide-Semiconductor Field-Effect Transistor）, so that from parameter variation view, quenching is beneficial in PMOS SET mitigation. The individual parameter analysis indicates that gate oxide thickness （TOXE） and channel length variation （XL） mostly affect SET response of combinational circuits. They bring 14.58% and 19.73% average WSET difference probabilities for no-quenching cases, and 105.56% and 123.32% for quenching cases.

Design of 700 V triple RESURF nLDMOS with low on-resistance

A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ.cm^2 is designed. Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region, the P-type layer of a triple RESURF nLDMOS is located within it. The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30% lower specific on-resistance at the same given breakdown voltage of 700 V. Detailed research of the influences of various parameters on breakdown voltage, specific on-resistance, as well as process tolerance is involved. The results may provide guiding principles for the design of triple RESURF nLDMOS.

The off-state gate isolation technique to improve ASET tolerance in differential analog design

A novel off-state gate RHBD technique to mitigate the single-event transient(SET)in the differential data path of analog circuit is demonstrated in this paper.Simulation results present that this off-state gate technique could exploit charge sharing in differential circuits and reduce differential mode voltage perturbation effectively.It is indicated that this technique is more effective to mitigate SET than the differential charge cancellation(DCC)technique with less penalty.

Performance of a double sided silicon strip detector as a transmission detector for heavy ions

The performance of a double sided silicon strip detector （DSSSD）, which is used for the position and energy detection of heavy ions, is reported. The analysis shows that although the incomplete charge collection （ICC） and charge sharing （CS） effects of the DSSSD give rise to a loss of energy resolution, the position information is recorded without ambiguity. Representations of ICC/CS events in the energy spectra are shown and their origins are confirmed by correlation analysis of the spectra from both the junction side and ohmic side of the DSSSD.

A Lesson From The Qvod Case

Four executives of Chinese video-sharing site Qvod Technology Co.Ltd.stood trial at the Haidian District People’s Court in Beijing on January 7-8 on charges of profiting from spreading pornographic content online.

A verifiable and efficient cross-chain calculation model for charging pile reputation

To solve the current situation of low vehicle-to-pile ratio,charging pile(CP)operators incorporate private CPs into the shared charging system.However,the introduction of private CP has brought about the problem of poor service quality.Reputation is a common service evaluation scheme,in which the third-party reputation scheme has the issue of single point of failure;although the blockchain-based reputation scheme solves the single point of failure issue,it also brings the challenges of storage and query efficiency.It is a feasible solution to classify and store information on multiple chains,and at this time,reputation needs to be calculated in a cross-chain mode.Crosschain reputation calculation faces the problems of correctness verification,integrity verification and efficiency.Therefore,this paper proposes a verifiable and efficient cross-chain calculation model for CP reputation.Specially,in this model,we propose a verifiable cross-chain contract calculation scheme that adopts polynomial commitment to solve the problems of polynomial damage and tampering that may be encountered in the crosschain process of outsourced polynomials,so as to ensure the integrity and correctness of polynomial calculations.In addition,the miner selection and incentive mechanism algorithm in this scheme ensures the correctness of extracted information when the outsourced polynomial is calculated on the blockchain.The security analysis and experimental results demonstrate that this scheme is feasible in practice.