A novel compact model for on-chip stacked transformers is presented.The proposed model topology gives a clear distinction to the eddy current,resistive and capacitive losses of the primary and secondary coils in the s...A novel compact model for on-chip stacked transformers is presented.The proposed model topology gives a clear distinction to the eddy current,resistive and capacitive losses of the primary and secondary coils in the substrate.A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided.The model is further verified by the excellent match between the measured and simulated S-parameters on the extracted parameters for a 1：1 stacked transformer manufactured in a commercial RF-CMOS technology.展开更多
Stacked chip scale package(SCSP) attracts more and more attentions in advanced packages application with light weight,thin and small size,high reliability,low power and high storage capability.However,more and more ph...Stacked chip scale package(SCSP) attracts more and more attentions in advanced packages application with light weight,thin and small size,high reliability,low power and high storage capability.However,more and more physical and electrical issues being caused by package-induced stress in SCSP were reported recently.The effect of structural factors,including die thickness,die attach film thickness,die attach film type,and spacer size on package induced stress,was investigated.Analyses were given based on simulation results and provide important suggestion for package design.展开更多
文摘A novel compact model for on-chip stacked transformers is presented.The proposed model topology gives a clear distinction to the eddy current,resistive and capacitive losses of the primary and secondary coils in the substrate.A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided.The model is further verified by the excellent match between the measured and simulated S-parameters on the extracted parameters for a 1：1 stacked transformer manufactured in a commercial RF-CMOS technology.
文摘Stacked chip scale package(SCSP) attracts more and more attentions in advanced packages application with light weight,thin and small size,high reliability,low power and high storage capability.However,more and more physical and electrical issues being caused by package-induced stress in SCSP were reported recently.The effect of structural factors,including die thickness,die attach film thickness,die attach film type,and spacer size on package induced stress,was investigated.Analyses were given based on simulation results and provide important suggestion for package design.
