Research on a High-Precision Delay Circuit in Data Acquisition Systems

This paper presents a novel precision delay circuit design for high-speed data acquisition systems. Many studies have suggested that various advanced electronic measurement apparatuses require that the delay circuit should have a high precision and a short delay interval. Practically, however, such measurement apparatuses are low in preci- sion and long in delay interval at present. The structure and function of a data acquisition system is introduced first; then the principle of ramp-based precision delay circuits and the digitally programmable delay generator is studied and the precision delay circuit is designed. The authors also demonstrated 8-bit programmable delay circuits with a timing pre- cision of 10 ps. Therefore the programmable precision delay circuit here presented has a higher precision, shorter inter- val and more detectable function than any other precision delay circuit.

Application study of dynamic voltage scaling policies

Based on the fundamental relationship among the circuit power, the circuit delay and the supply voltage, four theorems associated with the application of dynamic voltage scaling （DVS） policies are proposed and proved. First, the existence characteristics of the optimal supply voltage for a single task are proved, which suggests that the optimal supply voltage for the single task should be selected only within a one-dimensional term, and the corresponding task end time by the optimal supply voltage should be identical with its deadline. Then, it is pointed out that the minimum energy consumption that the DVS policy can obtain when completing a single task is certainly lower than that of the dynamic power management （DPM） policy or the combined DVS＋DPM policy under the same conditions. Finally, the theorem of energy consumption minimization for a multi-task group is proposed, which declares that it is necessary to keep the processor in the execution state during the whole task period to obtain the minimum energy consumption, while satisfying the deadline constraints of any task.

FPGA-based high resolution DPWM control circuit

Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.

A Novel Design of Mechanical Switch for the High Overload Environment

The internal structure of the inertial measurement unit(IMU)in active state is easily damaged in the high overload environment.So that the IMU is usually required to be powered within the disappearance of the high overload.In this paper,a mechanical switch is designed to enable the IMU based on the analysis of the impact of high overload on the power-supply circuit.In which,parameters of mechanical switch are determined through theoretical calculation and data analysis.The innovation of the proposed structure lies in that the mechanical switch is triggered through the high overload process and could provide a delay signal for the circuit.After all,the proposed switch is tested through mechanical simulation,impact test and practical test.The experimental results show that the designed mechanical switch can effectively and reliably provide the delay for the circuit and guarantee operation of the IMU under high overload.

A novel SOI-DTMOS structure from circuit performance considerations

The performance of a partially depleted silicon-on-insulator （PDSO1） dynamic threshold MOSFET （DT- MOS） is degraded by the large body capacitance and body resistance. Increasing silicon film thickness can reduce the body resistance greatly, but the body capacitance also increases significantly at the same time. To solve this problem, a novel SOl DTMOSFET structure （drain/source-on-local-insulator structure） is proposed. From ISE simulation, the improvement in delay, obtained by optimizing p-n junction depth and silicon film thickness, is very significant. At the same time, we find that the drive current increases significantly as the thickness of the silicon film increases. Furthermore, only one additional mask is needed to form the local SIMOX, and other fabrication processes are fully compatible with conventional CMOS/SOI technology.