Power is the major challenge threatening the progress of very large scale integration （VLSI） technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consump...Power is the major challenge threatening the progress of very large scale integration （VLSI） technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consumption, power supply noise, and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations, register placement actually strongly influences the clock network size. This paper describes a clock network design methodology that optimizes register placement. For a given cell placement result, incremental modifications are performed based on the clock skew specifications by moving registers toward preferred locations that may reduce the clock network size. At the same time, the side-effects to logic cell placement, such as signal net wirelength and critical path delay, are controlled. Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.展开更多
New synchronization algorithm and analysis of its convergence rate for clock oscillators in dynamical network with time-delays are presented.A network of nodes equipped with hardware clock oscillators with bounded dri...New synchronization algorithm and analysis of its convergence rate for clock oscillators in dynamical network with time-delays are presented.A network of nodes equipped with hardware clock oscillators with bounded drift is considered.Firstly,a dynamic synchronization algorithm based on consensus control strategy,namely fast averaging synchronization algorithm （FASA）,is presented to find the solutions to the synchronization problem.By FASA,each node computes the logical clock value based on its value of hardware clock and message exchange.The goal is to synchronize all the nodes＇ logical clocks as closely as possible.Secondly,the convergence rate of FASA is analyzed that proves it is related to the bound by a nondecreasing function of the uncertainty in message delay and network parameters.Then,FASA＇s convergence rate is proven by means of the robust optimal design.Meanwhile,several practical applications for FASA,especially the application to inverse global positioning system （IGPS） base station network are discussed.Finally,numerical simulation results demonstrate the correctness and efficiency of the proposed FASA.Compared FASA with traditional clock synchronization algorithms （CSAs）,the convergence rate of the proposed algorithm converges faster than that of the CSAs evidently.展开更多
As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of th...As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of the entire circuit system. Understanding the factors that influence the SET sensitivity of the CDN is crucial to achieving radiation hardening of the CDN and realizing the design of highly reliable ICs. In this paper, the influences of different sequential elements(D-flip-flops and D-latches, the two most commonly used sequential elements in modern synchronous digital systems) on the SET susceptibility of the CDN were quantitatively studied. Electrical simulation and heavy ion experiment results reveal that the CDN-SET-induced incorrect latching is much more likely to occur in DFF and DFF-based designs. This can supply guidelines for the design of IC with high reliability.展开更多
In order to detect the performance parameters of the network, for example, the network delay or delay jitter, the clock synchronization relations between the two hosts at two ends along the network must be calculated ...In order to detect the performance parameters of the network, for example, the network delay or delay jitter, the clock synchronization relations between the two hosts at two ends along the network must be calculated in advance. Then with the correct temporal relations between the two hosts, multimedia transmission along the network and display can occur by the proper order. A refined method based on Paxson's algorithm is proposed and testified. More accurate results can be attained by the method. By the way, the method can be used in a more complicated environment. Furthermore, an end-to-end network performance tester based on the proposed algorithm is designed and implemented.展开更多
The Controller Area Network (CAN) is a well established control network for automotive and automation control applications. Time-Triggered Controller Area Network (TTCAN) is a recent development which introduces a ses...The Controller Area Network (CAN) is a well established control network for automotive and automation control applications. Time-Triggered Controller Area Network (TTCAN) is a recent development which introduces a session layer,for message scheduling,to the existing CAN standard,which is a two layer standard comprising of a physical layer and a data link layer. TTCAN facilitates network communication in a time-triggered fashion,by introducing a Time Division Multiple Access style communication scheme. This allows deterministic network behavior,where maximum message latency times can be quantified and guaranteed. In order to solve the problem of determinate time latency and synchronization among several districted units in one auto panel CAN systems,this paper proposed a prototype design implementation for a shared-clock scheduler based on PIC18F458 MCU. This leads to improved CAN system performance and avoid the latency jitters and guarantee a deterministic communication pattern on the bus. The real runtime performance is satisfied.展开更多
The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically ab...The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically about 30% to 70% of the total dynamic (switching) power consumption. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. In this work, a new methodology is applied for gating the Flip flop by which the power will be reduced. The clock gating is employed to the pipelining stage flip flop which is active only during valid data are arrived. The methodology used in project named Selective Look-Ahead Clock Gating computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. Similarly to data-driven gating, it is capable of stopping the majority of redundant clock pulses. In this work, the circuit implementation of the various blocks of data driven clock gating is done and the results are observed. The proposed work is used for pipelining stage in microprocessor and DSP architectures. The proposed method is simulated using the quartus for cyclone 3 kit.展开更多
基金the National Natural Science Foundation of China (No. 60776026)
文摘Power is the major challenge threatening the progress of very large scale integration （VLSI） technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consumption, power supply noise, and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations, register placement actually strongly influences the clock network size. This paper describes a clock network design methodology that optimizes register placement. For a given cell placement result, incremental modifications are performed based on the clock skew specifications by moving registers toward preferred locations that may reduce the clock network size. At the same time, the side-effects to logic cell placement, such as signal net wirelength and critical path delay, are controlled. Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.
基金Sponsored by the Cooperation Building Foundation Project of Beijing Education Committee (100070
文摘New synchronization algorithm and analysis of its convergence rate for clock oscillators in dynamical network with time-delays are presented.A network of nodes equipped with hardware clock oscillators with bounded drift is considered.Firstly,a dynamic synchronization algorithm based on consensus control strategy,namely fast averaging synchronization algorithm （FASA）,is presented to find the solutions to the synchronization problem.By FASA,each node computes the logical clock value based on its value of hardware clock and message exchange.The goal is to synchronize all the nodes＇ logical clocks as closely as possible.Secondly,the convergence rate of FASA is analyzed that proves it is related to the bound by a nondecreasing function of the uncertainty in message delay and network parameters.Then,FASA＇s convergence rate is proven by means of the robust optimal design.Meanwhile,several practical applications for FASA,especially the application to inverse global positioning system （IGPS） base station network are discussed.Finally,numerical simulation results demonstrate the correctness and efficiency of the proposed FASA.Compared FASA with traditional clock synchronization algorithms （CSAs）,the convergence rate of the proposed algorithm converges faster than that of the CSAs evidently.
基金supported by the National Natural Science Foundation of China(No.61434007)the National Natural Science Foundation of China(No.61704192)
文摘As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of the entire circuit system. Understanding the factors that influence the SET sensitivity of the CDN is crucial to achieving radiation hardening of the CDN and realizing the design of highly reliable ICs. In this paper, the influences of different sequential elements(D-flip-flops and D-latches, the two most commonly used sequential elements in modern synchronous digital systems) on the SET susceptibility of the CDN were quantitatively studied. Electrical simulation and heavy ion experiment results reveal that the CDN-SET-induced incorrect latching is much more likely to occur in DFF and DFF-based designs. This can supply guidelines for the design of IC with high reliability.
文摘In order to detect the performance parameters of the network, for example, the network delay or delay jitter, the clock synchronization relations between the two hosts at two ends along the network must be calculated in advance. Then with the correct temporal relations between the two hosts, multimedia transmission along the network and display can occur by the proper order. A refined method based on Paxson's algorithm is proposed and testified. More accurate results can be attained by the method. By the way, the method can be used in a more complicated environment. Furthermore, an end-to-end network performance tester based on the proposed algorithm is designed and implemented.
文摘The Controller Area Network (CAN) is a well established control network for automotive and automation control applications. Time-Triggered Controller Area Network (TTCAN) is a recent development which introduces a session layer,for message scheduling,to the existing CAN standard,which is a two layer standard comprising of a physical layer and a data link layer. TTCAN facilitates network communication in a time-triggered fashion,by introducing a Time Division Multiple Access style communication scheme. This allows deterministic network behavior,where maximum message latency times can be quantified and guaranteed. In order to solve the problem of determinate time latency and synchronization among several districted units in one auto panel CAN systems,this paper proposed a prototype design implementation for a shared-clock scheduler based on PIC18F458 MCU. This leads to improved CAN system performance and avoid the latency jitters and guarantee a deterministic communication pattern on the bus. The real runtime performance is satisfied.
文摘The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically about 30% to 70% of the total dynamic (switching) power consumption. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. In this work, a new methodology is applied for gating the Flip flop by which the power will be reduced. The clock gating is employed to the pipelining stage flip flop which is active only during valid data are arrived. The methodology used in project named Selective Look-Ahead Clock Gating computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. Similarly to data-driven gating, it is capable of stopping the majority of redundant clock pulses. In this work, the circuit implementation of the various blocks of data driven clock gating is done and the results are observed. The proposed work is used for pipelining stage in microprocessor and DSP architectures. The proposed method is simulated using the quartus for cyclone 3 kit.
