In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LA...In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.展开更多
Using the tensor renormalization group method based on the higher-order singular value decomposition, we have studied the phase transitions of the five-state clock model on the square lattice. The temperature dependen...Using the tensor renormalization group method based on the higher-order singular value decomposition, we have studied the phase transitions of the five-state clock model on the square lattice. The temperature dependence of the specific heat indicates the system has two phase transitions, as verified clearly by the correlation function at three representative tem- peratures. By calculating the magnetic susceptibility, we obtained only the upper critical temperature as To2 = 0.9565（7）. Investigating the fixed-point tensor, we precisely locate the transition temperatures at Tcl = 0.9029（1） and Tc2 = 0.9520（1）, consistent well with the Monte Carlo and the density matrix renormalization group results.展开更多
A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can b...A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.展开更多
An asymmetry power clock,4 phase power clock supplying the power to the DSCRL(dual swing charge recovery logic) adiabatic circuit is presented.It is much simpler than the 6 phase power clock,symmetry power clock,us...An asymmetry power clock,4 phase power clock supplying the power to the DSCRL(dual swing charge recovery logic) adiabatic circuit is presented.It is much simpler than the 6 phase power clock,symmetry power clock,used in the DSCRL adiabatic circuit.Although the 4 phase power clock is simpler,the DSCRL adiabatic circuit still shows good performance and high efficiency of energy transfer and recovery.This conclusion has been proved by the result of the HSPICE simulation using the 0 6μm CMOS technology.展开更多
基于条件预充电技术,设计了一种高速低功耗真单相时钟触发器。在存在冗余开关活动的关键路径中,通过增加场效应管和控制条件,控制内部节点的冗余预充电活动;通过消除冗余结构,消除冗余的场效应管,从而改善电路结构,降低功耗和总功耗延...基于条件预充电技术,设计了一种高速低功耗真单相时钟触发器。在存在冗余开关活动的关键路径中,通过增加场效应管和控制条件,控制内部节点的冗余预充电活动;通过消除冗余结构,消除冗余的场效应管,从而改善电路结构,降低功耗和总功耗延时积。通用电路分析程序(simulation program with integrated circuit emphasis,HSPICE)仿真结果表明,在100 MHz的工作频率与低阈值电压下,触发器功耗低至158.6127 nW、总功耗延时积低至0.048735 fJ,电路具有正确的逻辑功能,且在功耗、延迟方面均优于近几年提出的电路。展开更多
In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low...In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.展开更多
近年来应用于中高能核物理实验的先进前端读出专用集成电路(application specific integrated circuit,ASIC)芯片呈现出越来越强的数字化趋势,可提高系统的集成度并降低功耗。论文研制了一种高计数率多通道时间测量与串行读出电路(high-...近年来应用于中高能核物理实验的先进前端读出专用集成电路(application specific integrated circuit,ASIC)芯片呈现出越来越强的数字化趋势,可提高系统的集成度并降低功耗。论文研制了一种高计数率多通道时间测量与串行读出电路(high-count rate multi-channel time measurement and serial readout circuit,HMTRC),可实现核事件去稀疏化、去随机化的读出。该电路主要包括了基于时钟分相技术的时间数字转化器、控制器、先进先出存储器和基于令牌环逻辑的轮询读出模块。HMTRC已被集成到一款自研的16通道前端读出ASIC芯片中,可测量和储存时间信息,并利用数字驱动的前端读出架构实现时间与能量信息同步读出。测试表明,时间分辨率好于2 ns,功能符合预期。展开更多
基金Supported by National Natural Science Foundation of China (No. 10405023)Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)
文摘In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
基金Project supported by the Fundamental Research Funds for the Central Universities,China(Grant No.531107040857)the Natural Science Foundation of Hunan Province,China(Grant No.851204035)the National Natural Science Foundation of China(Grant No.11774420)
文摘Using the tensor renormalization group method based on the higher-order singular value decomposition, we have studied the phase transitions of the five-state clock model on the square lattice. The temperature dependence of the specific heat indicates the system has two phase transitions, as verified clearly by the correlation function at three representative tem- peratures. By calculating the magnetic susceptibility, we obtained only the upper critical temperature as To2 = 0.9565（7）. Investigating the fixed-point tensor, we precisely locate the transition temperatures at Tcl = 0.9029（1） and Tc2 = 0.9520（1）, consistent well with the Monte Carlo and the density matrix renormalization group results.
文摘A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.
文摘An asymmetry power clock,4 phase power clock supplying the power to the DSCRL(dual swing charge recovery logic) adiabatic circuit is presented.It is much simpler than the 6 phase power clock,symmetry power clock,used in the DSCRL adiabatic circuit.Although the 4 phase power clock is simpler,the DSCRL adiabatic circuit still shows good performance and high efficiency of energy transfer and recovery.This conclusion has been proved by the result of the HSPICE simulation using the 0 6μm CMOS technology.
文摘基于条件预充电技术,设计了一种高速低功耗真单相时钟触发器。在存在冗余开关活动的关键路径中,通过增加场效应管和控制条件,控制内部节点的冗余预充电活动;通过消除冗余结构,消除冗余的场效应管,从而改善电路结构,降低功耗和总功耗延时积。通用电路分析程序(simulation program with integrated circuit emphasis,HSPICE)仿真结果表明,在100 MHz的工作频率与低阈值电压下,触发器功耗低至158.6127 nW、总功耗延时积低至0.048735 fJ,电路具有正确的逻辑功能,且在功耗、延迟方面均优于近几年提出的电路。
基金supported by the Fundamental Research Funds for the Central Universities under Grant No.2009JBM001
文摘In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.
文摘近年来应用于中高能核物理实验的先进前端读出专用集成电路(application specific integrated circuit,ASIC)芯片呈现出越来越强的数字化趋势,可提高系统的集成度并降低功耗。论文研制了一种高计数率多通道时间测量与串行读出电路(high-count rate multi-channel time measurement and serial readout circuit,HMTRC),可实现核事件去稀疏化、去随机化的读出。该电路主要包括了基于时钟分相技术的时间数字转化器、控制器、先进先出存储器和基于令牌环逻辑的轮询读出模块。HMTRC已被集成到一款自研的16通道前端读出ASIC芯片中,可测量和储存时间信息,并利用数字驱动的前端读出架构实现时间与能量信息同步读出。测试表明,时间分辨率好于2 ns,功能符合预期。
