2.5Gb/s Monolithic IC of Clock Recovery,Data Decision,and 1∶4 Demultiplexer

A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.

2.488 Gbit/s clock and data recovery circuit in 0.35 μm CMOS

The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.

2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.

Analysis and Design of a Phase Interpolator for Clock and Data Recovery

In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new encoding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator. To alleviate this undesired effect, two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phase interpolator is lmW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone output phase and good linearity.

A 2 .5Gb/s GaAs MESFET Clock Recovery and Decision Circuit

A 2 5Gb/s depletion mode GaAs MESFET clock recovery and decision circuit is described,which applies to the optical fiber communication.The circuit consists of a clock recovery circuit,including a preprocessor,phase detector(PD),low pass filter(LPF) and voltage controlled oscillator(VCO) and a decision circuit,including a comparator and a latch.The SPICE simulation result confirms the high frequency 2 5GHz of the clock recovery and the high speed 2 5Gb/s of the decision circuit.The 2 5Gb/s decision circuit has proved to be able to deal with the input signal and produce a digital output signal after it being sampled by a clock signal.

A 5-Gbit/s monolithically-integrated low-power clock recovery circuit in 0.18-μm CMOS

In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.

Performance analysis of a novel chip tracking loop used for regenerative pseudo-noise ranging clock recovery

To improve the performance of composite pseudo-noise （PN） code clock recovery in a regenerative PN ranging system at a low symbol signal-to-noise ratio （SNR）, a novel chip tracking loop （CTL） used for regenerative PN ranging clock recovery is adopted. The CTL is a modified data transition tracking loop （DTTL）. The difference between them is that the Q channel output of the CTL is directly multiplied by a clock component, while that of the DTTL is multiplied by the Ⅰ channel transition detector output. Under the condition of a quasi-squareware PN ranging code, the tracking （ mean square timing jitter） performance of the CTL is analyzed. The tracking performances of the CTL and the DTTL, are compared over a wide range of symbol SNRs. The result shows that the CTL and the DTTL have the same performance at a large symbol SNR, while at a low symbol SNR, the former offers a noticeable enhancement.

Control of period-one oscillation for all-optical clock division and clock recovery by optical pulse injection driven semiconductor laser

The period-one oscillation produced by an external optical pulse injection driven semiconductor laser is applied to clock recovery and frequency division. By adjusting the repetition rate or injection power of the external injection optical pulses to lock the different harmonic frequencies of the period-one state, the clock recovery and the frequency division （the second and third frequency divisions） are achieved experimentally. In addition, in frequency locking ranges of 2 GHz and 1.9 GHz, the second and third frequency divisions are obtained with the phase noise lower than 100 dBc/Hz, respectively. Our experimental results are consistent well with the numerical simulations.

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.

Modeling for Ethernet passive optical network receiver

A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a clock and data recovery＇ circuit （CDR）. Each sub-model is constructed based on the architecture of a circuit. The noise and jitter in each block such as shot noise, thermal noise, deterministic and random jitter are also considered. The performance of the whole receiver can be evaluated by the simulation of the behavior model, which is faster than the ordinary circuit model and more accurate than the analytical model. The whole model is implemented with C ＋＋ and simulated in Microsoft Visual C ＋＋ 6. 0. Using the Monte Carlo method, the EPON receiver is simulated. The simulation results show a good agreement with experimental ones.

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a tripleinductive transimpedance amplifier(TIA), direct current(DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers(VGA), and a reference-less clock and data recovery(CDR) circuit with built-in equalization technique. The TIA/VGA frontend measurement results demonstrate 72-dB? transimpedance gain, 20.4-GHz-3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10-12 BER at 26 Gb/s for a 2;-1 PRBS input with a-7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.

High-precision high-sensitivity clock recovery circuit for a mobile payment application

This paper presents a fully integrated carrier clock recovery circuit for a mobile payment application. The architecture is based on a sampling-detection module and a charge pump phase locked loop. Compared with clock recovery in conventional 13.56 MHz transponders, this circuit can recover a high-precision consecutive carrier clock from the on/off keying （OOK） signal sent by interrogators. Fabricated by a SMIC 0.18-μm EEPROM CMOS process, this chip works from a single power supply as low as 1.5 V. Measurement results show that this circuit provides 0.34% frequency deviation and 8 mV sensitivity.

Clock recovery from NRZ data at 10 Gb/s using SOA loop mirror and mode-locked fiber ring laser based on SOA

All optical clock recovery from non return-to-zero （NRZ） data using an semiconductor optical amplifier （SOA） loop mirror and a mode-locked SOA fibcr lascr is firstly schematically explained and experimentally demonstrated at 10 Gb/s. Furthermore, the pulse quality of tile recovered cluck is cffcctivcly improved by using a continuous-wave （CW） assist light in the gain region of SOA, through which the amplitude modulation is reduced from 57.2% to 8.47%. This scheme is a promising method for clock recovery from NRZ data in the future all-optical communication networks.

Design of a 6.25 Gbps backplane SerDes with adaptive decision feedback equalization

A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a half-rate four-tap decision feedback equalizer （DFE）. The equalizer used the Signsign least mean-squared （SS-LMS） algorithm to realize the coefficient adaptation. An automatic gain control （AGC） amplifier with the sign least mean-squared （S-LMS） algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery （BB-CR） is adopted. A third order phase loop loek （PLL） model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34＂ FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.

Tone Modulation in a Passive OTDM Multiplexer for Clock Recovery from a 160 Gbit/s OTDM Signal

Tone modulation in a passive OTDM multiplexer for clock recovery from a 160-Gbit/s OTDM signal by using a base-rate receiver is demonstrated. We performed synchronous demultiplexing in back-to-back arrangement and optical sampling after 320-km transmission.

A 2.5-Gb/s fully-integrated,low-power clock and recovery circuit in 0.18-μm CMOS

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery （CDR） circuit has been designed and fabricated in SMIC＇s 0.18-μm CMOS technology. The Pottbiicker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 × 440μm2, and consumes a power of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV. It has a pull-in range of 800 MHz, and a phase noise of-111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components.

All-optical clock recovery from 10-Gb/s NRZ data and NRZ to RZ format conversion

A non-return-to-zero （NRZ） to pseudo-return-to-zero （PRZ） converter consisting of a semiconductor optical amplifier （SOA） and an arrayed waveguide grating （AWG） is proposed, by which the enhancement of clock frequency component and clock-to-data suppression ratio of the XRZ data are evidently achieved. All- optical clock recovery from XRZ data at 10 Gb/s is successfully demonstrated with the proposed XRZ-to- PRZ converter and a mode-locked SOA fiber laser. Furthermore, XRZ-to-RZ format conversion of 10 Gb/s is realized bv using the recovered clock as the control light of terahertz optical asymmetric demultiplexer （TOAD）, which further proves that the proposed clock recovery scheme is applicable.

Multi-Rate SerDes Transceiver for IEEE 1394b Applications

This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2^ including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.

A 10 Gb/s burst-mode clock and data recovery circuit

We introduce a gated oscillator based on XONR/XOR cells and illustrate its working process. A halfrate BM-CDR circuit based on the proposed oscillator is designed, and the design is implemented in SMIC 0.13 μm CMOS technology occupying an area of 675 ×25 μm2. The measured results show that this circuit can recover clock and data from each 10 Gbit/s burst-mode data packet within 5 bits, and the recovered data pass eye-mask test defined in IEEE standard 802.3av.

A 750 MHz semi-digital clock and data recovery circuit with 10^(-12) BER

A semi-digital clock and data recovery （CDR） is presented. In order to lower CDR trace jitter and decrease loop latency, an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13 μm standard 1PSM CMOS process, our CDR is integrated into a high speed serial and de-serial （SERDES） chip. Measurement results of the chip show that the CDR can trace the phase of the input data well and the RiMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency, while the bit error rate of the recovery data is less than 10 × 10^-12.