Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance ...Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance IC designs. In contrast to most of the traditional studies that handle this problem with clock routing or buffer insertion strategy, this paper proposes a novel register clustering methodology in generating the leaf level topology of the clock tree to reduce the power consumption. Three register clustering algorithms called KMR, KSR and GSR are developed and a comprehensive study of them is discussed in this paper. Meanwhile~ a buffer allocation algorithm is proposed to satisfy the slew constraint within the clusters at a minimum cost of power consumption. We integrate our algorithms into a classical clock tree synthesis （CTS） flow to test the register clustering methodology on ISPD 2010 benchmark circuits. Experimental results show that all the three register clustering algorithms achieve more than 20% reduction in power consumption without affecting the skew and the maximum latency of the clock tree. As the most effective method among the three algorithms, GSR algorithm achieves a 31% reduction in power consumption as well as a 4% reduction in skew and a 5% reduction in maximum latency. Moreover, the total runtime of the CTS flow with our register clustering algorithms is significantly reduced by almost an order of magnitude.展开更多
为了降低芯片的功耗,提高芯片的性能和可靠性,在传统数字芯片物理设计流程基础上,提出一种新的低功耗物理设计方法,包括布局(Placement)阶段采用SAIF文件进行低功耗的协同优化,并在布局结果基础上,通过手动配置时钟单元摆放来减小缓冲...为了降低芯片的功耗,提高芯片的性能和可靠性,在传统数字芯片物理设计流程基础上,提出一种新的低功耗物理设计方法,包括布局(Placement)阶段采用SAIF文件进行低功耗的协同优化,并在布局结果基础上,通过手动配置时钟单元摆放来减小缓冲单元插入的方式进行低功耗的时钟树设计。结果表明:通过新的低功耗设计可以大幅改善芯片功耗,在布局阶段,芯片功耗降为原来的90.6%,建立时间的最差违例值由-6.021降为-0.880;时钟树综合(clock tree synthesis,CTS)阶段,功耗优化效果显著,时钟网络功耗降为原来的73.1%,总功耗降为原来的86.2%;时序得到改善,建立时间的违例总条数降为原来的12.5%,总违例值降为原来的3.0%,保持时间的违例总条数降为原来的39.8%,总违例值降为原来的7.5%。展开更多
Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Cus...Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.展开更多
基金This work was supported by the National Natural Science Foundation of China under Grant No. 61274031.
文摘Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance IC designs. In contrast to most of the traditional studies that handle this problem with clock routing or buffer insertion strategy, this paper proposes a novel register clustering methodology in generating the leaf level topology of the clock tree to reduce the power consumption. Three register clustering algorithms called KMR, KSR and GSR are developed and a comprehensive study of them is discussed in this paper. Meanwhile~ a buffer allocation algorithm is proposed to satisfy the slew constraint within the clusters at a minimum cost of power consumption. We integrate our algorithms into a classical clock tree synthesis （CTS） flow to test the register clustering methodology on ISPD 2010 benchmark circuits. Experimental results show that all the three register clustering algorithms achieve more than 20% reduction in power consumption without affecting the skew and the maximum latency of the clock tree. As the most effective method among the three algorithms, GSR algorithm achieves a 31% reduction in power consumption as well as a 4% reduction in skew and a 5% reduction in maximum latency. Moreover, the total runtime of the CTS flow with our register clustering algorithms is significantly reduced by almost an order of magnitude.
文摘为了降低芯片的功耗,提高芯片的性能和可靠性,在传统数字芯片物理设计流程基础上,提出一种新的低功耗物理设计方法,包括布局(Placement)阶段采用SAIF文件进行低功耗的协同优化,并在布局结果基础上,通过手动配置时钟单元摆放来减小缓冲单元插入的方式进行低功耗的时钟树设计。结果表明:通过新的低功耗设计可以大幅改善芯片功耗,在布局阶段,芯片功耗降为原来的90.6%,建立时间的最差违例值由-6.021降为-0.880;时钟树综合(clock tree synthesis,CTS)阶段,功耗优化效果显著,时钟网络功耗降为原来的73.1%,总功耗降为原来的86.2%;时序得到改善,建立时间的违例总条数降为原来的12.5%,总违例值降为原来的3.0%,保持时间的违例总条数降为原来的39.8%,总违例值降为原来的7.5%。
基金Project supported by the Hi-Tech Research and Development Pro-gram (863) of China (No. 2002AA1Z1140)the Fok Ying TongEducation Foundation (No. 94031), China
文摘Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.
