High Efficient Reconfigurable and Self Testable Architecture for Sensor Node

Sensor networks are regularly sent to monitor certain physical properties that run in length from divisions of a second to many months or indeed several years.Nodes must advance their energy use for expanding network lifetime.The fault detection of the network node is very significant for guaranteeing the correctness of monitoring results.Due to different network resource constraints and malicious attacks,security assurance in wireless sensor networks has been a difficult task.The implementation of these features requires larger space due to distributed module.This research work proposes new sensor node architecture integrated with a self-testing core and cryptoprocessor to provide fault-free operation and secured data transmission.The proposed node architecture was designed using Verilog programming and implemented using the Xilinx ISE tool in the Spartan 3E environment.The proposed system supports the real-time application in the range of 33 nanoseconds.The obtained results have been compared with the existing Microcontroller-based system.The power consumption of the proposed system consumes only 3.9 mW,and it is only 24%percentage of AT mega-based node architecture.

Reconfigurable Logic Design of CORDIC Based FFT Architecture for 5G Communications

There are numerous goals in next-generation cellular networks(5G),which is expected to be available soon.They want to increase data rates,reduce end-to-end latencies,and improve end-user service quality.Modern networks need to change because there has been a significant rise in the number of base stations required to meet these needs and put the operators’low-cost constraints to the test.Because it can withstand interference from other wireless networks,and Adaptive Complex Multicarrier Modulation(ACMM)system is being looked at as a possible choice for the 5th Generation(5G)of wireless networks.Many arithmetic units need to be used on the hardware side of multicarrier systems to do the pulse-shaping filters and inverse FFT.The main goal of this study is to adapt complex multicarrier modulation(ACMM)for baseband transmission with low complexity and the ability to change it.We found that this is the first recon-figurable architecture that lets you choose how many subcarriers a subband has while still having the same amount of hardware resources as before.Also,under the new design with a single selection line,it selects from a set of filters.The baseband modulating signal is evaluated and tested using a Field-Programmable Gate Array(FPGA)device.This device is available from a commercial source.New technology outperforms current technology in terms of computational com-plexity,simple design,and ease of implementation.Additionally,it has a higher power spectrum density,spectral efficiency,a lower bit error rate,and a higher peak to average power ratio than existing technology.

Deep reinforcement learning based multi-level dynamic reconfiguration for urban distribution network:a cloud-edge collaboration architecture

With the construction of the power Internet of Things(IoT),communication between smart devices in urban distribution networks has been gradually moving towards high speed,high compatibility,and low latency,which provides reliable support for reconfiguration optimization in urban distribution networks.Thus,this study proposed a deep reinforcement learning based multi-level dynamic reconfiguration method for urban distribution networks in a cloud-edge collaboration architecture to obtain a real-time optimal multi-level dynamic reconfiguration solution.First,the multi-level dynamic reconfiguration method was discussed,which included feeder-,transformer-,and substation-levels.Subsequently,the multi-agent system was combined with the cloud-edge collaboration architecture to build a deep reinforcement learning model for multi-level dynamic reconfiguration in an urban distribution network.The cloud-edge collaboration architecture can effectively support the multi-agent system to conduct“centralized training and decentralized execution”operation modes and improve the learning efficiency of the model.Thereafter,for a multi-agent system,this study adopted a combination of offline and online learning to endow the model with the ability to realize automatic optimization and updation of the strategy.In the offline learning phase,a Q-learning-based multi-agent conservative Q-learning(MACQL)algorithm was proposed to stabilize the learning results and reduce the risk of the next online learning phase.In the online learning phase,a multi-agent deep deterministic policy gradient(MADDPG)algorithm based on policy gradients was proposed to explore the action space and update the experience pool.Finally,the effectiveness of the proposed method was verified through a simulation analysis of a real-world 445-node system.

Architecture, challenges and applications of dynamic reconfigurable computing

As a computing paradigm that combines temporal and spatial computations,dynamic reconfigurable computing provides superiorities of flexibility,energy efficiency and area efficiency,attracting interest from both academia and industry.However,dynamic reconfigurable computing is not yet mature because of several unsolved problems.This work introduces the concept,architecture,and compilation techniques of dynamic reconfigurable computing.It also discusses the existing major challenges and points out its potential applications.

Virtual reconfigurable architecture for evolving combinational logic circuits

A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.

A reconfigurable low-cost memory-efficient VLSI architecture for video scaling

A runtime reconfigurable very-large-scale integration （VLSI） architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a wide range of applications from broadcast, medical imaging and high-resolution video effects to video surveillance, and video conferencing. Many algorithms have been proposed for these applications, such as piecewise polynomial kernels and windowed sinc kernels. The sum of three shifted versions of a B-spline function, whose weights can be adjusted for different applications, is adopted as the main filter. The proposed algorithm is confirmed to be effective on image scaling ap- plications and also verified by many widely acknowledged image quality measures. The reconfigu- rable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array （FPGA） devices. The scaling factor can be changed on-the-fly, and the filter can also be changed during runtime within a unifying framework.

Design of an adaptive precoding/STBC baseband transceiver on a reconfigurable architecture

Precoding and space-time block coding （STBC）techniques using the uniform channel decomposition （UCD）are proposed to improve the bit error rate （BER） of themultiple-antenna communication system, but at a cost of areduced data rate. In order to achieve a higher overall systemperformance, a novel adaptive transceiver architecture whichflexibly combines both UCD and UCD ＋ STBC technologies isproposed. The channel state information （CSI） feedback pathwas added to the precoder to select which coding method wasto be used, i.e. UCD alone or UCD ＋ STBC. With thesmaller constellation sizes, Matlab simulation results showthat, the adaptive transceiver architecture will select the UCD-only mode under the higher SNR conditions in order to achievea higher bit rate. The UCD ＋ STBC mode will be selectedunder the lower SNR conditions （e. g., SNR 〈 10 dB） inorder to maintain good BER performance at the cost of areduced data rate. This architecture was implemented andverified using both UMC 0.18 ASIC process technology and aXilinx xc4vlx Virtex-4 FPGA at 150 MHz. The simulationresults demonstrate that the required number of reconfigurablearithmetic unit slices grows linearly with the channel matrixsize, while the number of adder array unit and reconfigurablelogic unit slices increases slightly with the constellation size.

Distributed MPC for Reconfigurable Architecture Systems via Alternating Direction Method of Multipliers

This paper investigates the distributed model predictive control(MPC)problem of linear systems where the network topology is changeable by the way of inserting new subsystems,disconnecting existing subsystems,or merely modifying the couplings between different subsystems.To equip live systems with a quick response ability when modifying network topology,while keeping a satisfactory dynamic performance,a novel reconfiguration control scheme based on the alternating direction method of multipliers(ADMM)is presented.In this scheme,the local controllers directly influenced by the structure realignment are redesigned in the reconfiguration control.Meanwhile,by employing the powerful ADMM algorithm,the iterative formulas for solving the reconfigured optimization problem are obtained,which significantly accelerate the computation speed and ensure a timely output of the reconfigured optimal control response.Ultimately,the presented reconfiguration scheme is applied to the level control of a benchmark four-tank plant to illustrate its effectiveness and main characteristics.

A VLIW Architecture Stream Cryptographic Processor for Information Security

As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.

Smart Service System(SSS)：A Novel Architecture Enabling Coordination of Heterogeneous Networking Technologies and Devices for Internet of Things

In Internet of Things(IoT), the devices or terminals are connected with each other, which can be very diverse over the wireless networks. Unfortunately, the current devices are not designed to communicate with the collocated devices which employ different communication technologies. Consequently, the communication between these devices will be realized only by using the gateway nodes. This will cause the inefficient use of wireless resources. Therefore, in this paper, a smart service system(SSS) architecture is proposed, which consists of smart service terminal(SST), and smart service network(SSN), to realize the Io T in a general environment with diverse communication networks, devices, and services. The proposed architecture has the following advantages: i) the devices in this architecture cover multiple types of terminals and sensor-actuator devices; ii) the communications network therein is a converged network, and will coordinate multiple kinds of existing and emerging networks. This converged network offers ubiquitous access for various sensors and terminals; iii) the architecture has services and applications covering all smart service areas. It also provides theadaptability to new services and applications. A SSS architecture-based smart campus system was developed and deployed. Evaluation experiments of the proposed smart campus system demonstrate the SSS's advantages over the existing counterparts, and verify the effectiveness of the proposed architecture.

THE RESEARCH AND DESIGN OF RECONFIGURABLE COMPUTING FOR BLOCK CIPHER

This paper describes a new specialized Reconfigurable Cryptographic for Block ciphersArchitecture(RCBA).Application-specific computation pipelines can be configured according to thecharacteristics of the block cipher processing in RCBA,which delivers high performance for crypto-graphic applications.RCBA adopts a coarse-grained reconfigurable architecture that mixes the ap-propriate amount of static configurations with dynamic configurations.RCBA has been implementedbased on Altera’s FPGA,and representative algorithms of block cipher such as DES,Rijndael and RC6have been mapped on RCBA architecture successfully.System performance has been analyzed,andfrom the analysis it is demonstrated that the RCBA architecture can achieve more flexibility and ef-ficiency when compared with other implementations.

A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator

In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor itself rather than computation;this decreases the energy efficiency. Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) and registers). We propose a novel dynamically reconfigurable accelerator “DYNaSTA” composed of a dynamically reconfigurable data path and static ALU arrays. The static ALU arrays process instructions in parallel without registers and improve energy efficiency. The dynamically reconfigurable data path includes registers and many switches dynamically reconfigured to resolve operand dependencies between instructions mapped on the static ALU array, and forwards appropriate operands to the static ALU array. Therefore, the DYNaSTA accelerator has more flexibility while improving the energy efficiency compared with the conventional dynamically reconfigurable accelerators. We simulated the power consumption of the proposed DYNaSTA accelerator and measured the fabricated chip. As a result, the power consumption was reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13 times compared to a general RISC microprocessor.

Loop Subgraph-Level Greedy Mapping Algorithm for Grid Coarse-Grained Reconfigurable Array

To solve the problem of grid coarse-grained reconfigurable array task mapping under multiple constraints,we propose a Loop Subgraph-Level Greedy Mapping(LSLGM)algorithm using parallelism and processing element fragmentation.Under the constraint of a reconfigurable array,the LSLGM algorithm schedules node from a ready queue to the current reconfigurable cell array block.After mapping a node,its successor’s indegree value will be dynamically updated.If its successor’s indegree is zero,it will be directly scheduled to the ready queue;otherwise,the predecessor must be dynamically checked.If the predecessor cannot be mapped,it will be scheduled to a blocking queue.To dynamically adjust the ready node scheduling order,the scheduling function is constructed by exploiting factors,such as node number,node level,and node dependency.Compared with the loop subgraph-level mapping algorithm,experimental results show that the total cycles of the LSLGM algorithm decreases by an average of 33.0%(PEA44)and 33.9%(PEA_(7×7)).Compared with the epimorphism map algorithm,the total cycles of the LSLGM algorithm decrease by an average of 38.1%(PEA_(4×4))and 39.0%(PEA_(7×7)).The feasibility of LSLGM is verified.

子连接有源可重构智能表面辅助的宽带无蜂窝网络能效优化

面对无蜂窝网络中超密集基站部署产生的高功耗问题,提出了一种基于子连接有源可重构智能表面辅助的宽带无蜂窝网络系统。考虑有源智能超表面最大功率约束、放大因子约束和基站端最大功率约束,构建了一个联合基站和可重构智能表面波束优化的能效最大化问题。由于所形成的优化问题非凸,提出了一种交替优化方案将原问题转化为多个子问题,进而利用块坐标下降、拉格朗日对偶变换、多维复二次变换等方法将每个子问题转化为凸优化问题,通过交替求解每个子问题最终获得原问题的解。仿真结果验证了所提方案的有效性。

一种基于三角数分解的可配置2-D卷积器优化方法

多尺寸2-D卷积通过特征提取在检测、分类等计算机视觉任务中发挥着重要作用。然而,目前缺少一种高效的可配置2-D卷积器设计方法,这限制了卷积神经网络(CNN)模型在边缘端的部署和应用。该文基于乘法管理以及奇平方数的三角数分解方法,提出一种高性能、高适应性的卷积核尺寸可配置的2-D卷积器。所提2-D卷积器包含一定数量的处理单元(PE)以及相应的控制单元,前者负责运算任务,后者负责管理乘法运算的组合,二者结合以实现不同尺寸的卷积。具体地,首先根据应用场景确定一个奇数列表,列表中为2-D卷积器所支持的尺寸,并利用三角数分解得到对应的三角数列表;其次,根据三角数列表和计算需求,确定PE的总数量;最后,基于以小凑大的方法,确定PE的互连方式,完成电路设计。该可配置2-D卷积器通过Verilog硬件描述语言(HDL)设计实现,由Vivado 2 022.2在XCZU7EG板卡上进行仿真和分析。实验结果表明,相比同类方法,该文所提可配置2-D卷积器,乘法资源利用率得到显著提升,由20%~50%提升至89%,并以514个逻辑单元实现1 500 MB/s的吞吐率,具有广泛的适用性。

Reconfigurable logic and in-sensor encryption operations in an asymmetrically tunable van der Waals heterostructure

Reconfigurable devices can be used to achieve multiple logic operation and intelligent optical sensing with low power consumption,which is promising candidates for new generation electronic and optoelectronic integrated circuits.However,the versatility is still limited and need to be extended by the device architectures design.Here,we report an asymmetrically gate two-dimensional(2D)van der Waals heterostructure with hybrid dielectric layer SiO_(2)/hexagonal boron nitride(h-BN),which enable rich function including reconfigurable logic operation and in-sensor information encryption enabled by both volatile and non-volatile optoelectrical modulation.When the partial gate is grounded,the non-volatile light assisted electrostatic doping endowed partially reconfigurable doping between n-type and p-type,which allow the switching of logic XOR and not implication(NIMP).When the global gate is grounded,additionally taking the optical signal as another input signal,logic AND and OR is realized by combined regulation of the light and localized gate voltage.Depending on the high on/off current ratio approaching 105 and reliable&switchable logic gate,in-sensor information encryption and decryption is demonstrated by manipulating the logic output.Hence,these results provide strong extension for current reconfigurable electronic and optoelectronic devices.

Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning

To apply a quasi-cyclic low density parity check(QC-LDPC)to different scenarios,a data-stream driven pipelined macro instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm.The data-level parallelism is improved by instructions to dynamically configure the multi-core computing units.Simultaneously,an intelligent adjustment strategy based on a programmable wake-up controller(WuC)is designed so that the computing mode,operating voltage,and frequency of the QC-LDPC algorithm can be adjusted.This adjustment can improve the computing efficiency of the processor.The QC-LDPC processors are verified on the Xilinx ZCU102 field programmable gate array(FPGA)board and the computing efficiency is measured.The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency.The maximum efficiency can reach up to 12.18 Gbit/(s·W),which is more flexible than existing state-of-the-art processors for QC-LDPC.

基于软件化雷达的可重构信息处理架构设计

为实现雷达信息处理系统快速研制与升级,本文提出了基于软件化雷达的可重构信息处理架构。首先,本文分析了国内外软件化可重构雷达的研究现状,随后提出了基于通用化物理层与中间件层、微服务组件层和应用层的可重构信息处理架构设计方案。最后通过测试实验和理论计算验证了可重构架构的高可扩展性、可维护性和可靠性。本文提出的架构为现代可重构数字化雷达设计提供了基础和保障。

A Novel Reconfigurable Data-Flow Architecture for Real Time Video Processing

This paper describes a dynamically reconfigurable data-flow hardware architecture optimized for the computation of image and video. It is a scalable hierarchically organized parallel architecture that consists of data-flow clusters and finite-state machine （FSM） controllers. Each cluster contains various kinds of ceils that are optimized for video processing. Furthermore, to facilitate the design process, we provide a C-like language for design specification and associated design tools. Some video applications have been implemented in the architecture to demonstrate the applicability and flexibility of the architecture. Experimental results show that the architecture, along with its video applications, can be used in many real-time video processing.

面向低精度神经网络的数据流体系结构优化

数据流架构的执行方式与神经网络算法具有高度匹配性,能充分挖掘数据的并行性.然而,随着神经网络向更低精度的发展,数据流架构的研究并未面向低精度神经网络展开,在传统数据流架构部署低精度(INT8,INT4或者更低)神经网络时,会面临3个问题:1)传统数据流架构的计算部件数据通路与低精度数据不匹配,无法体现低精度神经网络的性能和能效优势;2)向量化并行计算的低精度数据在片上存储中要求顺序排列,然而它在片外存储层次中是分散排列的,使得数据的加载和写回操作变得复杂,传统数据流架构的访存部件无法高效支持这种复杂的访存模式;3)传统数据流架构中使用双缓冲机制掩盖数据的传输延迟,但是,当传输低精度数据时,传输带宽的利用率显著降低,导致计算延迟无法掩盖数据传输延迟,双缓冲机制面临失效风险,进而影响数据流架构的性能和能效.为解决这3个问题,设计了面向低精度神经网络的数据流加速器DPU_Q.首先,设计了灵活可重构的计算单元,根据指令的精度标志位动态重构数据通路,一方面能高效灵活地支持多种低精度数据运算,另一方面能进一步提高计算并行性和吞吐量.另外,为解决低精度神经网络复杂的访存模式,设计了Scatter引擎,该引擎将在低层次或者片外存储中地址空间离散分布的低精度数据进行拼接、预处理,以满足高层次或者片上存储对数据排列的格式要求.同时,Scatter引擎能有效解决传输低精度数据时带宽利用率低的问题,解决了双缓冲机制失效的问题.最后,从软件方面提出了基于数据流执行模式的低精度神经网络映射算法,兼顾负载均衡的同时能对权重、激活值数据进行充分复用,减少了访存和数据流图节点间的数据传输开销.实验表明,相比于同精度的GPU(Titan Xp)、数据流架构(Eyeriss)和低精度神经网络加速器(BitFusion),DPU_Q分别获得3.18倍、6.05倍、1.52倍的性能提升和4.49倍、1.6倍、1.13倍的能效提升.